add hreset

1 files changed, 22 insertions, 1 deletions

diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs
index b7387d9..c9a2de0 100644
--- a/src/protected_mode/mod.rs
+++ b/src/protected_mode/mod.rs
@@ -1996,6 +1996,9 @@ pub enum Opcode {
     ENCODEKEY256,
     LOADIWKEY,
 
+    // unsure
+    HRESET,
+
     // 3dnow
     FEMMS,
     PI2FW,
@@ -4676,6 +4679,7 @@ enum OperandCode {
     ModRM_0xf30f38df = OperandCodeBuilder::new().read_modrm().special_case(49).bits(),
     ModRM_0xf30f38fa = OperandCodeBuilder::new().read_modrm().special_case(50).bits(),
     ModRM_0xf30f38fb = OperandCodeBuilder::new().read_modrm().special_case(51).bits(),
+    ModRM_0xf30f3af0 = OperandCodeBuilder::new().read_modrm().special_case(52).bits(),
 //    ModRM_0x660f3a = OperandCodeBuilder::new().read_modrm().special_case(52).bits(),
 //    ModRM_0x0f38 = OperandCodeBuilder::new().read_modrm().special_case(53).bits(),
 //    ModRM_0x0f3a = OperandCodeBuilder::new().read_modrm().special_case(54).bits(),
@@ -6806,7 +6810,14 @@ fn read_0f38_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord {
 }
 
 fn read_0f3a_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord {
-    if prefixes.rep() || prefixes.repnz() {
+    if prefixes.rep() {
+        return match opcode {
+            0xf0 => OpcodeRecord(Interpretation::Instruction(Opcode::HRESET), OperandCode::ModRM_0xf30f3af0),
+            _ => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+        };
+    }
+
+    if prefixes.repnz() {
         return OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing);
     }
 
@@ -8521,6 +8532,16 @@ fn unlikely_operands<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as y
             instruction.regs[0].bank = RegisterBank::D;
             instruction.regs[1].bank = RegisterBank::D;
         }
+        OperandCode::ModRM_0xf30f3af0 => {
+            let modrm = words.next().ok().ok_or(DecodeError::ExhaustedInput)?;
+            if modrm & 0xc0 != 0xc0 {
+                return Err(DecodeError::InvalidOpcode);
+                // invalid
+            }
+            instruction.opcode = Opcode::HRESET;
+            instruction.imm = read_num(words, 1)?;
+            instruction.operands[0] = OperandSpec::ImmU8;
+        }
         OperandCode::G_mm_Ed => {
             instruction.regs[0].bank = RegisterBank::MM;
             instruction.regs[0].num &= 0b111;