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authoriximeow <me@iximeow.net>2023-12-15 17:26:59 -0800
committeriximeow <me@iximeow.net>2023-12-15 17:26:59 -0800
commit003183a4ce31cfb718f4e4083d32c845352c2321 (patch)
treee6931eb0d6baa7eaa99a2386e8d13a6037fd421f /src/protected_mode/vex.rs
parent792eb993a87fab799b3a6659c7750f2221608cbf (diff)
more RegSpec constructor validation, fix bug in x86_64 1b reg specs
* the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be constructed in two ways that produce "identical" `RegSpec` that are.. not. e.g. `RegSpec::al() != Regspec::rb(0)` even though `RegSpec::al().name() == RegSpec::rb(0).name()`. this corrects the `rb` constructor at least, but instructions like `4830c0` and `30c0` still produce incompatible versions of `al`. * also fix register numbering used explicit qword-sized RegSpec constructors, r12 and r13 used to produce r8 and r9
Diffstat (limited to 'src/protected_mode/vex.rs')
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