diff options
| author | iximeow <me@iximeow.net> | 2021-10-10 14:40:55 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2021-10-10 14:40:55 -0700 |
| commit | ed5c76a0f8e92656539f305b9b7ea5e032517f36 (patch) | |
| tree | cdb68a927f2f6fbe5fea284464e3b1d09cf02a60 /src/real_mode | |
| parent | 148fc10ed26fb025ceb291ae6c03515ee578cbeb (diff) | |
support endbr{32,64}
Diffstat (limited to 'src/real_mode')
| -rw-r--r-- | src/real_mode/display.rs | 4 | ||||
| -rw-r--r-- | src/real_mode/mod.rs | 33 |
2 files changed, 33 insertions, 4 deletions
diff --git a/src/real_mode/display.rs b/src/real_mode/display.rs index 10640a4..258f5d9 100644 --- a/src/real_mode/display.rs +++ b/src/real_mode/display.rs @@ -1406,6 +1406,8 @@ const MNEMONICS: &[&'static str] = &[ "setssbsy", "clrssbsy", "rstorssp", + "endbr64", + "endbr32", // TDX "tdcall", @@ -3233,6 +3235,8 @@ impl <T: fmt::Write, Y: YaxColors> Colorize<T, Y> for Opcode { Opcode::SETSSBSY | Opcode::CLRSSBSY | Opcode::RSTORSSP | + Opcode::ENDBR64 | + Opcode::ENDBR32 | Opcode::AESDEC | Opcode::AESDECLAST | Opcode::AESENC | diff --git a/src/real_mode/mod.rs b/src/real_mode/mod.rs index 45dd7a3..92c0592 100644 --- a/src/real_mode/mod.rs +++ b/src/real_mode/mod.rs @@ -2077,6 +2077,8 @@ pub enum Opcode { SETSSBSY, CLRSSBSY, RSTORSSP, + ENDBR64, + ENDBR32, // TDX TDCALL, @@ -4905,9 +4907,7 @@ enum OperandCode { ModRM_0x0f73 = OperandCodeBuilder::new().read_modrm().special_case(57).bits(), ModRM_0xf20f78 = OperandCodeBuilder::new().read_modrm().special_case(58).bits(), ModRM_0x660f78 = OperandCodeBuilder::new().read_modrm().special_case(59).bits(), -// ModRM_0x660f12 = OperandCodeBuilder::new().read_modrm().special_case(58).bits(), -// ModRM_0x660f16 = OperandCodeBuilder::new().read_modrm().special_case(59).bits(), -// ModRM_0x660f71 = OperandCodeBuilder::new().read_modrm().special_case(60).bits(), + ModRM_0xf30f1e = OperandCodeBuilder::new().special_case(60).bits(), // ModRM_0x660f72 = OperandCodeBuilder::new().read_modrm().special_case(61).bits(), // ModRM_0x660f73 = OperandCodeBuilder::new().read_modrm().special_case(62).bits(), // ModRM_0x660fc7 = OperandCodeBuilder::new().read_modrm().special_case(63).bits(), @@ -6395,7 +6395,7 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x1b => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), 0x1c => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), 0x1d => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), - 0x1e => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), + 0x1e => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::ModRM_0xf30f1e), 0x1f => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), 0x20 => OpcodeRecord(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), @@ -8785,6 +8785,31 @@ fn unlikely_operands< instruction.operand_count = 3; } + OperandCode::ModRM_0xf30f1e => { + let modrm = read_modrm(words)?; + match modrm { + 0xfa => { + instruction.opcode = Opcode::ENDBR64; + instruction.operand_count = 0; + }, + 0xfb => { + instruction.opcode = Opcode::ENDBR32; + instruction.operand_count = 0; + }, + _ => { + let (sz, bank) = if instruction.prefixes.operand_size() { + (4, RegisterBank::D) + } else { + (2, RegisterBank::W) + }; + instruction.operands[1] = OperandSpec::RegRRR; + instruction.operands[0] = read_E(words, instruction, modrm, sz, sink)?; + instruction.regs[0] = + RegSpec::from_parts((modrm >> 3) & 7, bank); + instruction.operand_count = 2; + } + }; + } OperandCode::G_E_xmm_Ub => { let modrm = read_modrm(words)?; |