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authoriximeow <me@iximeow.net>2021-07-04 15:03:30 -0700
committeriximeow <me@iximeow.net>2021-07-04 15:03:30 -0700
commit723cbb61c1a8a7aa03fa4e2fc9081c5eb16f53e8 (patch)
treec865fe893c09cfd2d9fadbccfde9f49262870cd2 /src/shared/evex.in
parentff9760b94936de929777f9730ac1568ac26bf4d5 (diff)
support avx512 registers >=16
Diffstat (limited to 'src/shared/evex.in')
-rw-r--r--src/shared/evex.in14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/shared/evex.in b/src/shared/evex.in
index f848808..6446b52 100644
--- a/src/shared/evex.in
+++ b/src/shared/evex.in
@@ -71,6 +71,20 @@ pub(crate) fn read_evex<T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch a
let (opcode, operand_code) = table[entry].1[index_lower];
instruction.opcode = opcode;
read_evex_operands(words, instruction, operand_code)?;
+ if instruction.prefixes.evex_unchecked().rp() {
+ instruction.regs[0].num |= 0b10000;
+ if ![RegisterBank::X, RegisterBank::Y, RegisterBank::Z].contains(&instruction.regs[0].bank) {
+ return Err(DecodeError::InvalidOperand);
+ }
+ }
+ if instruction.prefixes.evex_unchecked().vex().x() {
+ if instruction.operands.contains(&OperandSpec::RegMMM) {
+ instruction.regs[1].num |= 0b10000;
+ if ![RegisterBank::X, RegisterBank::Y, RegisterBank::Z].contains(&instruction.regs[1].bank) {
+ return Err(DecodeError::InvalidOperand);
+ }
+ }
+ }
if instruction.prefixes.evex_unchecked().vex().compressed_disp() {
let overridden_size = match instruction.opcode {
Opcode::VPEXPANDB => Some(1),