diff options
author | iximeow <me@iximeow.net> | 2023-07-06 02:04:24 -0700 |
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committer | iximeow <me@iximeow.net> | 2023-07-06 02:04:24 -0700 |
commit | d48909eaa7263e5395d2124f8b20117cd0e1e981 (patch) | |
tree | c4f241199b84fe3c7554d24700a2bc069747ad64 /src | |
parent | 74bacb4c07e1872c235c0eb85ef9e13ad372c9fd (diff) |
defer initial assignment of regs and operands as much as possible
not a huge improvement, but something
Diffstat (limited to 'src')
-rw-r--r-- | src/long_mode/mod.rs | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 34db72a..c0e89e5 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -6531,9 +6531,9 @@ fn read_with_annotations< // const RAXRAXRAXRAX: [RegSpec; 4] = [RegSpec::rax(); 4]; // default x86_64 registers to `[rax; 4]` - instruction.regs[0] = RegSpec::rax(); // = RAXRAXRAXRAX; - // default operands to [RegRRR, Nothing, Nothing, Nothing] - instruction.operands = unsafe { core::mem::transmute(0x00_00_00_01) }; +// instruction.regs = RAXRAXRAXRAX; + instruction.regs[1] = RegSpec::rax(); + instruction.regs[2] = RegSpec::rax(); let record: OperandCode = if self.read_opc_hotpath(nextb, &mut nextb, &mut next_rec, words, instruction, sink)? { next_rec.1 @@ -6859,10 +6859,12 @@ fn read_operands< } else { read_M(words, instruction, modrm, sink)? }; - instruction.operands[1] = mem_oper; if !operand_code.has_reg_mem() { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; + } else { + instruction.operands[1] = mem_oper; + instruction.operands[0] = OperandSpec::RegRRR; } return Ok(()); } @@ -6938,10 +6940,12 @@ fn read_operands< } else { read_M(words, instruction, modrm, sink)? }; - instruction.operands[1] = mem_oper; if !operand_code.has_reg_mem() { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; + } else { + instruction.operands[1] = mem_oper; + instruction.operands[0] = OperandSpec::RegRRR; } } @@ -7095,6 +7099,10 @@ fn read_operands< return Ok(()); } + if !operand_code.has_read_E() { + instruction.operands = unsafe { core::mem::transmute(0x00_00_00_01) }; + } + // match operand_code { match operand_code.operand_case_handler_index() { OperandCase::Internal | OperandCase::Gv_M | |