diff options
| author | iximeow <me@iximeow.net> | 2023-07-09 15:55:18 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2023-07-09 15:55:21 -0700 |
| commit | 483612635a70e009f1e38e967994dbc2d5bc453d (patch) | |
| tree | 0760d52f1d7f9804a0ceaeb146397730638a207a /src | |
| parent | dfeff40ef53fd47a578994250846920e532a87b3 (diff) | |
more matches to be mad at and turn into lookups instead
Diffstat (limited to 'src')
| -rw-r--r-- | src/long_mode/mod.rs | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 0be4e68..7986650 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -6996,12 +6996,18 @@ fn read_operands< } instruction.imm = read_imm_ivq(words, bank as u8)?; - instruction.operands[1] = match bank as u8 { - 2 => OperandSpec::ImmI16, - 4 => OperandSpec::ImmI32, - 8 => OperandSpec::ImmI64, - _ => unsafe { unreachable_unchecked() } - }; + const TBL: [OperandSpec; 9] = [ + OperandSpec::ImmI16, + OperandSpec::ImmI16, + OperandSpec::ImmI16, + OperandSpec::ImmI32, + OperandSpec::ImmI32, + OperandSpec::ImmI64, + OperandSpec::ImmI64, + OperandSpec::ImmI64, + OperandSpec::ImmI64, + ]; + instruction.operands[1] = *TBL.get(bank as usize).unwrap_or_else(|| unsafe { unreachable_unchecked() } ); sink.record( words.offset() as u32 * 8 - (8 * bank as u8 as u32), words.offset() as u32 * 8 - 1, |