diff options
| author | iximeow <me@iximeow.net> | 2023-01-29 17:44:05 -0800 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2023-07-04 19:01:38 -0700 |
| commit | 62102819adcadf8253f27d5ea06953d1400c2dfe (patch) | |
| tree | 7d46030862fa1ab0b692c3b0b99397fbd8f2eeee /src | |
| parent | 0a4004c44c3170c9b4a94bd6a53c7a4600299a8f (diff) | |
line up Opcode values for simple translation from opc bytes
Diffstat (limited to 'src')
| -rw-r--r-- | src/long_mode/display.rs | 20 | ||||
| -rw-r--r-- | src/long_mode/mod.rs | 49 |
2 files changed, 37 insertions, 32 deletions
diff --git a/src/long_mode/display.rs b/src/long_mode/display.rs index bb5f682..181ea14 100644 --- a/src/long_mode/display.rs +++ b/src/long_mode/display.rs @@ -357,9 +357,19 @@ const MNEMONICS: &[&'static str] = &[ "adc", "sbb", "and", - "xor", "sub", + "xor", "cmp", + + "rol", + "ror", + "rcl", + "rcr", + "shl", + "shr", + "sal", + "sar", + "invalid", "xadd", "bt", @@ -409,15 +419,7 @@ const MNEMONICS: &[&'static str] = &[ "movzx", "movsx", "movsxd", - "sar", - "sal", - "shr", "shrd", - "shl", - "rcr", - "rcl", - "ror", - "rol", "inc", "dec", "hlt", diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index de6d701..0ba806e 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -1073,14 +1073,22 @@ const XSAVE: [Opcode; 10] = [ #[non_exhaustive] #[repr(u32)] pub enum Opcode { - ADD, + ADD = 0, OR, ADC, SBB, AND, - XOR, SUB, + XOR, CMP, + ROL = 8, + ROR, + RCL, + RCR, + SHL, + SHR, + SAL, + SAR, Invalid, XADD, BT, @@ -1130,15 +1138,7 @@ pub enum Opcode { MOVZX, MOVSX, MOVSXD, - SAR, - SAL, - SHR, SHRD, - SHL, - RCR, - RCL, - ROR, - ROL, INC, DEC, HLT, @@ -5394,16 +5394,19 @@ fn base_opcode_map(v: u8) -> Opcode { } } -const BITWISE_OPCODE_MAP: [Opcode; 8] = [ - Opcode::ROL, - Opcode::ROR, - Opcode::RCL, - Opcode::RCR, - Opcode::SHL, - Opcode::SHR, - Opcode::SAL, - Opcode::SAR -]; +fn bitwise_opcode_map(v: u8) -> Opcode { + match v { + 0 => Opcode::ROL, + 1 => Opcode::ROR, + 2 => Opcode::RCL, + 3 => Opcode::RCR, + 4 => Opcode::SHL, + 5 => Opcode::SHR, + 6 => Opcode::SAL, + 7 => Opcode::SAR, + _ => { unsafe { unreachable_unchecked() } } + } +} #[derive(Copy, Clone, Debug, PartialEq, Eq)] enum Interpretation { @@ -7304,7 +7307,7 @@ fn read_operands< }, 5 => { instruction.operands[0] = mem_oper; - instruction.opcode = BITWISE_OPCODE_MAP[((modrm >> 3) & 7) as usize].clone(); + instruction.opcode = bitwise_opcode_map((modrm >> 3) & 7); sink.record( modrm_start + 3, modrm_start + 5, @@ -7323,7 +7326,7 @@ fn read_operands< } 7 => { instruction.operands[0] = mem_oper; - instruction.opcode = BITWISE_OPCODE_MAP[((modrm >> 3) & 7) as usize].clone(); + instruction.opcode = bitwise_opcode_map((modrm >> 3) & 7); sink.record( modrm_start + 3, modrm_start + 5, @@ -7342,7 +7345,7 @@ fn read_operands< } 9 => { instruction.operands[0] = mem_oper; - instruction.opcode = BITWISE_OPCODE_MAP[((modrm >> 3) & 7) as usize].clone(); + instruction.opcode = bitwise_opcode_map((modrm >> 3) & 7); sink.record( modrm_start + 3, modrm_start + 5, |