diff options
author | iximeow <me@iximeow.net> | 2020-01-15 01:49:42 -0800 |
---|---|---|
committer | iximeow <me@iximeow.net> | 2020-01-15 01:49:42 -0800 |
commit | 53a6a79595e100b16b85d75676bcfee56cbd40f0 (patch) | |
tree | c4d1179ef3b214a0177b67dc53128424dc5bce48 /src | |
parent | 95fbfd0165a6ed2aac9098ab015a25de68030a3b (diff) |
add 660f6* series instructions as well as 660f70
this adds in some missing sse2 instructions in the alternate secondary
opcode map. because these were missing, instructions were incorrectly
decoded from the 0f opcode map, yielding mmx-operand versions of
themselves (usually)
there are undoubtedly more missing sse2 instructions from the 660f map.
Diffstat (limited to 'src')
-rw-r--r-- | src/display.rs | 8 | ||||
-rw-r--r-- | src/lib.rs | 50 |
2 files changed, 41 insertions, 17 deletions
diff --git a/src/display.rs b/src/display.rs index 4c97d5c..f3400f6 100644 --- a/src/display.rs +++ b/src/display.rs @@ -278,6 +278,7 @@ impl fmt::Display for Opcode { match self { &Opcode::POPCNT => write!(f, "popcnt"), &Opcode::MOVDQU => write!(f, "movdqu"), + &Opcode::MOVDQA => write!(f, "movdqa"), &Opcode::MOVQ => write!(f, "movq"), &Opcode::CMPSS => write!(f, "cmpss"), &Opcode::CMPSD => write!(f, "cmpsd"), @@ -564,6 +565,7 @@ impl fmt::Display for Opcode { &Opcode::POR => write!(f, "por"), &Opcode::PSADBW => write!(f, "psadbw"), &Opcode::PSHUFW => write!(f, "pshufw"), + &Opcode::PSHUFD => write!(f, "pshufd"), &Opcode::PSLLD => write!(f, "pslld"), &Opcode::PSLLQ => write!(f, "psllq"), &Opcode::PSLLW => write!(f, "psllw"), @@ -586,6 +588,8 @@ impl fmt::Display for Opcode { &Opcode::PUNPCKLBW => write!(f, "punpcklbw"), &Opcode::PUNPCKLDQ => write!(f, "punpckldq"), &Opcode::PUNPCKLWD => write!(f, "punpcklwd"), + &Opcode::PUNPCKLQDQ => write!(f, "punpcklqdq"), + &Opcode::PUNPCKHQDQ => write!(f, "punpckhqdq"), &Opcode::PXOR => write!(f, "pxor"), &Opcode::RCPPS => write!(f, "rcpps"), &Opcode::RSM => write!(f, "rsm"), @@ -1306,6 +1310,7 @@ impl <T: fmt::Write, Color: fmt::Display, Y: YaxColors<Color>> Colorize<T, Color Opcode::PMULUDQ | Opcode::POR | Opcode::PSADBW | + Opcode::PSHUFD | Opcode::PSHUFW | Opcode::PSHUFB | Opcode::PSLLD | @@ -1578,6 +1583,8 @@ impl <T: fmt::Write, Color: fmt::Display, Y: YaxColors<Color>> Colorize<T, Color Opcode::PUNPCKLBW | Opcode::PUNPCKLDQ | Opcode::PUNPCKLWD | + Opcode::PUNPCKLQDQ | + Opcode::PUNPCKHQDQ | Opcode::PACKSSDW | Opcode::PACKSSWB | Opcode::PACKUSWB | @@ -1602,6 +1609,7 @@ impl <T: fmt::Write, Color: fmt::Display, Y: YaxColors<Color>> Colorize<T, Color Opcode::MOVSLDUP | Opcode::MOVDQ2Q | Opcode::MOVDQU | + Opcode::MOVDQA | Opcode::MOVQ | Opcode::MOVQ2DQ | Opcode::MOVSHDUP | @@ -636,6 +636,7 @@ pub enum Opcode { JMPE, POPCNT, MOVDQU, + MOVDQA, MOVQ, CMPSS, CMPSD, @@ -744,6 +745,7 @@ pub enum Opcode { POR, PSADBW, PSHUFW, + PSHUFD, PSLLD, PSLLQ, PSLLW, @@ -766,6 +768,8 @@ pub enum Opcode { PUNPCKLBW, PUNPCKLDQ, PUNPCKLWD, + PUNPCKLQDQ, + PUNPCKHQDQ, PXOR, RCPPS, RSM, @@ -3009,24 +3013,24 @@ const OPCODE_660F_MAP: [OpcodeRecord; 256] = [ OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x60 - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), + OpcodeRecord(Interpretation::Instruction(Opcode::PUNPCKLBW), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PUNPCKLWD), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PUNPCKLDQ), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PACKSSWB), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PCMPGTB), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PCMPGTW), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PCMPGTD), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PACKUSWB), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PUNPCKHBW), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PUNPCKHWD), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PUNPCKHDQ), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PACKSSDW), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PUNPCKLQDQ), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::PUNPCKHQDQ), OperandCode::G_E_xmm), + OpcodeRecord(Interpretation::Instruction(Opcode::MOVQ), OperandCode::G_xmm_Eq), + OpcodeRecord(Interpretation::Instruction(Opcode::MOVDQA), OperandCode::G_E_xmm), // 0x70 - OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), + OpcodeRecord(Interpretation::Instruction(Opcode::PSHUFD), OperandCode::G_E_xmm_Ib), OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), @@ -5155,6 +5159,18 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, } } }, + OperandCode::G_E_xmm_Ib => { + let modrm = read_modrm(&mut bytes_iter, length)?; + + instruction.operands[1] = read_E_xmm(&mut bytes_iter, instruction, modrm, length)?; + instruction.modrm_rrr = RegSpec { bank: RegisterBank::X, num: (modrm >> 3) & 7 }; + instruction.operands[0] = OperandSpec::RegRRR; + instruction.imm = + read_num(&mut bytes_iter, 1)? as u8 as u64; + *length += 1; + instruction.operands[2] = OperandSpec::ImmI8; + instruction.operand_count = 3; + }, OperandCode::G_E_mm_Ib => { let modrm = read_modrm(&mut bytes_iter, length)?; |