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| author | iximeow <me@iximeow.net> | 2019-03-17 01:04:40 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2020-01-12 16:10:13 -0800 |
| commit | cdce6ba84e8aa5972fb4b5820fab87ce1b197d77 (patch) | |
| tree | 06d5bc626df9241ed4a17e55e05f97763e0db6b4 /test/bench.rs | |
| parent | 9e07d5cc25c33842115a88ee4ef406b9d7d30907 (diff) | |
several tweaks:
* DisplacementI32 was never used, DisplacementU64 added to distinguish 8
and 4 byte addresses
* Added setCC instructions
* Fix sign extension bug for displacement as interpreted by E operands
* Add operand code support for a0,a1,a2,a3 movs
* Add operand code support for Ivs, Ibs
* Complete support for 0x81
* Clean up tests
Diffstat (limited to 'test/bench.rs')
0 files changed, 0 insertions, 0 deletions