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authoriximeow <me@iximeow.net>2024-06-24 12:48:45 -0700
committeriximeow <me@iximeow.net>2024-06-24 12:48:45 -0700
commit1b8019d5b39a05c109399b8628a1082bfec79755 (patch)
tree2183199b4da0ec1cf3d88f9f1b75498e0d86da27 /test/long_mode/operand.rs
parentb8a294db5ae6831c54be368e41fa8418a6f73bcb (diff)
rename most operand variants, make them structy rather than tupley
Diffstat (limited to 'test/long_mode/operand.rs')
-rw-r--r--test/long_mode/operand.rs16
1 files changed, 8 insertions, 8 deletions
diff --git a/test/long_mode/operand.rs b/test/long_mode/operand.rs
index a47e6c8..0faa1c3 100644
--- a/test/long_mode/operand.rs
+++ b/test/long_mode/operand.rs
@@ -3,19 +3,19 @@ use yaxpeax_x86::MemoryAccessSize;
#[test]
fn register_widths() {
- assert_eq!(Operand::Register(RegSpec::rsp()).width(), Some(8));
- assert_eq!(Operand::Register(RegSpec::esp()).width(), Some(4));
- assert_eq!(Operand::Register(RegSpec::sp()).width(), Some(2));
- assert_eq!(Operand::Register(RegSpec::cl()).width(), Some(1));
- assert_eq!(Operand::Register(RegSpec::ch()).width(), Some(1));
- assert_eq!(Operand::Register(RegSpec::gs()).width(), Some(2));
+ assert_eq!(Operand::Register { reg: RegSpec::rsp() }.width(), Some(8));
+ assert_eq!(Operand::Register { reg: RegSpec::esp() }.width(), Some(4));
+ assert_eq!(Operand::Register { reg: RegSpec::sp() }.width(), Some(2));
+ assert_eq!(Operand::Register { reg: RegSpec::cl() }.width(), Some(1));
+ assert_eq!(Operand::Register { reg: RegSpec::ch() }.width(), Some(1));
+ assert_eq!(Operand::Register { reg: RegSpec::gs() }.width(), Some(2));
}
#[test]
fn memory_widths() {
// the register operand directly doesn't report a size - it comes from the `Instruction` for
- // which this is an operand.
- assert_eq!(Operand::RegDeref(RegSpec::rsp()).width(), None);
+ // which this is an operand .
+ assert_eq!(Operand::MemDeref { base: RegSpec::rsp() }.width(), None);
fn mem_size_of(data: &[u8]) -> MemoryAccessSize {
let decoder = InstDecoder::default();