diff options
| author | iximeow <me@iximeow.net> | 2024-08-16 21:21:16 -0700 |
|---|---|---|
| committer | iximeow <me@iximeow.net> | 2025-06-01 09:21:37 +0000 |
| commit | 08eed360fea81ab9328fd0859b813ee01937b5b1 (patch) | |
| tree | c379847e969d479c13c29f46864465cf2969d9cb /test/long_mode | |
| parent | 681262f4472ba4f452446e86012ce629b849d8d9 (diff) | |
expand isa feature selection to more bits
this is backed by the new IsaSettings trait. the existing InstDecoders
are unchanged, except that they implement this new trait.
also add new `DecodeEverything` structs with `IsaSettings` impls that
are unconditionally set to permit anything the decoder can be configured
to conditionally accept or reject.
in the process, add new `_3dnow` flag and stop accepting 3dnow
instructions in uarch-specific decoder settings that would not have
3dnow instructions.
update AMD microarchitectures and cross-ref chip directory
Diffstat (limited to 'test/long_mode')
| -rw-r--r-- | test/long_mode/mod.rs | 24 | ||||
| -rw-r--r-- | test/long_mode/regspec.rs | 4 |
2 files changed, 19 insertions, 9 deletions
diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs index 917d16a..9493a63 100644 --- a/test/long_mode/mod.rs +++ b/test/long_mode/mod.rs @@ -3449,13 +3449,23 @@ fn test_sse4a() { #[test] fn test_3dnow() { - test_display(&[0x0f, 0x0f, 0xe0, 0x8a], "pfnacc mm4, mm0"); - test_display(&[0x0f, 0x0f, 0x38, 0x8e], "pfpnacc mm7, qword [rax]"); - test_display(&[0x65, 0x67, 0x65, 0x65, 0x0f, 0x0e], "femms"); - test_display(&[0x3e, 0xf3, 0x2e, 0xf2, 0x0f, 0x0f, 0x64, 0x93, 0x93, 0xa4], "pfmax mm4, qword [rbx + rdx * 4 - 0x6d]"); - test_display(&[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], "pi2fw mm6, qword [rax - 0x5]"); - test_display(&[0x66, 0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); - test_display(&[0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); + fn test_instr(bytes: &[u8], text: &'static str) { + test_display_under(&InstDecoder::minimal().with_3dnow(), bytes, text); + test_display_under(&InstDecoder::default(), bytes, text); + test_invalid_under(&InstDecoder::minimal(), bytes); + test_invalid_under(&InstDecoder::minimal(), bytes); + test_invalid_under(&yaxpeax_x86::long_mode::uarch::amd::k8(), bytes); + test_invalid_under(&yaxpeax_x86::long_mode::uarch::intel::netburst(), bytes); + } + + test_instr(&[0x0f, 0x0f, 0xe0, 0x8a], "pfnacc mm4, mm0"); + test_instr(&[0x0f, 0x0f, 0x38, 0x8e], "pfpnacc mm7, qword [rax]"); + test_instr(&[0x65, 0x67, 0x65, 0x65, 0x0f, 0x0e], "femms"); + test_instr(&[0x3e, 0xf3, 0x2e, 0xf2, 0x0f, 0x0f, 0x64, 0x93, 0x93, 0xa4], "pfmax mm4, qword [rbx + rdx * 4 - 0x6d]"); + test_instr(&[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], "pi2fw mm6, qword [rax - 0x5]"); + test_instr(&[0x66, 0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); + test_instr(&[0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); + test_instr(&[0x0f, 0x0e], "femms"); } // first appeared in tremont diff --git a/test/long_mode/regspec.rs b/test/long_mode/regspec.rs index 220435f..81416ff 100644 --- a/test/long_mode/regspec.rs +++ b/test/long_mode/regspec.rs @@ -11,7 +11,7 @@ fn test_hash() { let _: HashMap<RegSpec, u64> = HashMap::new(); } -#[cfg(features="fmt")] +#[cfg(feature="fmt")] #[test] fn test_labels() { assert_eq!(RegSpec::rip().name(), "rip"); @@ -22,7 +22,7 @@ fn test_labels() { assert_eq!(RegSpec::al().name(), "al"); } -#[cfg(features="fmt")] +#[cfg(feature="fmt")] #[test] fn test_bank_names() { assert_eq!(RegSpec::al().class().name(), "byte"); |