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author | iximeow <me@iximeow.net> | 2023-12-16 13:26:48 -0800 |
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committer | iximeow <me@iximeow.net> | 2023-12-16 13:26:48 -0800 |
commit | 110f797005cca70e18cbcc0975397d26d8045245 (patch) | |
tree | a3ff79c0c3a7519d00e19d213447c268614cef00 /test/protected_mode/opcode.rs | |
parent | 85668b222582ef1edae537beea452d5e1c933389 (diff) |
fix opportunity for unhandled register synonyms
registers `al`, `cl`, `dl`, and `bl` could have two different
representations - with `rex.w` and without. these two forms of `RegSpec`
would not compare equal, nor has the same, so for code relying on
`RegSpec` to faithfully represent a 1-1 mapping to x86 registers, these
synonyms would introduce bugs in register analysis.
for example, in `yaxpeax-core`, this would result in instructions
writing to `rex.w al` not being visible as definitions for a future
read of `!rex.w al`.
fix this in `x86_64` code, add new test cases about the confusion,
adjust register names to make this situation more clearly a bug, and
introduce two new fuzz targets that would have helped spot this error.
Diffstat (limited to 'test/protected_mode/opcode.rs')
0 files changed, 0 insertions, 0 deletions