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author | iximeow <me@iximeow.net> | 2021-03-21 01:02:00 -0700 |
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committer | iximeow <me@iximeow.net> | 2021-03-21 01:21:55 -0700 |
commit | a493b4d267c4fb6a042cf071301c8885196b4a91 (patch) | |
tree | 9be24cf43e2fef9f48d6f88e0b7716eb5f66ccca /test/protected_mode/regspec.rs | |
parent | 0c8dccaf591748e6acb9b437d69ba028e59a73cf (diff) |
rewrite 0f-based instruction handling
this is... a more significant rewrite than i expected yaxpeax-x86 to
ever need. it turns out that capstone is extremely permissive about
duplicative 66/f2/f3 prefixes to the point that the implemented prefex
handling was unsalvageable.
while this replaces the *0f* opcode tables, i haven't profiled these
changes. it's possible this is a net improvement for single-byte
opcodes, it could be a net loss. code size may be severely impacted.
there is still work to do.
but this in total gets very close to iced/xed/zydis parity, far more
than before.
also adds several small extensions, gfni, 3dnow, enqcmd, invpcid, some
of cet, and a few missing avx instructions.
Diffstat (limited to 'test/protected_mode/regspec.rs')
0 files changed, 0 insertions, 0 deletions