expand isa feature selection to more bits

this is backed by the new IsaSettings trait. the existing InstDecoders
are unchanged, except that they implement this new trait.

also add new `DecodeEverything` structs with `IsaSettings` impls that
are unconditionally set to permit anything the decoder can be configured
to conditionally accept or reject.

in the process, add new `_3dnow` flag and stop accepting 3dnow
instructions in uarch-specific decoder settings that would not have
3dnow instructions.

update AMD microarchitectures and cross-ref chip directory

1 files changed, 2 insertions, 2 deletions

diff --git a/test/protected_mode/regspec.rs b/test/protected_mode/regspec.rs
index aeca086..8f32142 100644
--- a/test/protected_mode/regspec.rs
+++ b/test/protected_mode/regspec.rs
@@ -11,7 +11,7 @@ fn test_hash() {
     let _: HashMap<RegSpec, u64> = HashMap::new();
 }
 
-#[cfg(features="fmt")]
+#[cfg(feature="fmt")]
 #[test]
 fn test_labels() {
     assert_eq!(RegSpec::eip().name(), "eip");
@@ -20,7 +20,7 @@ fn test_labels() {
     assert_eq!(RegSpec::al().name(), "al");
 }
 
-#[cfg(features="fmt")]
+#[cfg(feature="fmt")]
 #[test]
 fn test_bank_names() {
     assert_eq!(RegSpec::al().class().name(), "byte");