diff options
| -rw-r--r-- | src/long_mode/display.rs | 56 | ||||
| -rw-r--r-- | src/long_mode/mod.rs | 684 | ||||
| -rw-r--r-- | src/long_mode/vex.rs | 212 | ||||
| -rw-r--r-- | test/long_mode/mod.rs | 1998 |
4 files changed, 1655 insertions, 1295 deletions
diff --git a/src/long_mode/display.rs b/src/long_mode/display.rs index 4702861..f235c6a 100644 --- a/src/long_mode/display.rs +++ b/src/long_mode/display.rs @@ -3307,13 +3307,13 @@ impl Instruction { const MEM_SIZE_STRINGS: [&'static str; 64] = [ "byte", "word", "BUG", "dword", "BUG", "BUG", "BUG", "qword", - "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "xmmword", + "far", "mword", "BUG", "BUG", "BUG", "BUG", "BUG", "xmmword", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "ymmword", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", - "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "zmmword", + "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "ptr", "zmmword", ]; fn contextualize_intel<T: fmt::Write, Y: YaxColors>(instr: &Instruction, colors: &Y, _address: u64, _context: Option<&NoContext>, out: &mut T) -> fmt::Result { @@ -3343,57 +3343,19 @@ fn contextualize_intel<T: fmt::Write, Y: YaxColors>(instr: &Instruction, colors: if instr.operand_count > 0 { out.write_str(" ")?; - if let Some(prefix) = instr.segment_override_for_op(0) { - write!(out, "{}:", prefix)?; - } - let x = Operand::from_spec(instr, instr.operands[0]); if x.is_memory() { out.write_str(MEM_SIZE_STRINGS[instr.mem_size as usize - 1])?; out.write_str(" ")?; } + + if let Some(prefix) = instr.segment_override_for_op(0) { + write!(out, "{}:", prefix)?; + } x.colorize(colors, out)?; for i in 1..instr.operand_count { match instr.opcode { - Opcode::MOVSX_b | - Opcode::MOVZX_b => { - match &instr.operands[i as usize] { - &OperandSpec::Nothing => { - return Ok(()); - }, - &OperandSpec::RegMMM => { - out.write_str(", ")?; - } - _ => { - out.write_str(", byte ")?; - if let Some(prefix) = instr.segment_override_for_op(i) { - write!(out, "{}:", prefix)?; - } - } - } - let x = Operand::from_spec(instr, instr.operands[i as usize]); - x.colorize(colors, out)? - }, - Opcode::MOVSX_w | - Opcode::MOVZX_w => { - match &instr.operands[i as usize] { - &OperandSpec::Nothing => { - return Ok(()); - }, - &OperandSpec::RegMMM => { - out.write_str(", ")?; - } - _ => { - out.write_str(", word ")?; - if let Some(prefix) = instr.segment_override_for_op(i) { - write!(out, "{}:", prefix)?; - } - } - } - let x = Operand::from_spec(instr, instr.operands[i as usize]); - x.colorize(colors, out)?; - }, _ => { match &instr.operands[i as usize] { &OperandSpec::Nothing => { @@ -3401,14 +3363,14 @@ fn contextualize_intel<T: fmt::Write, Y: YaxColors>(instr: &Instruction, colors: }, _ => { out.write_str(", ")?; - if let Some(prefix) = instr.segment_override_for_op(i) { - write!(out, "{}:", prefix)?; - } let x = Operand::from_spec(instr, instr.operands[i as usize]); if x.is_memory() { out.write_str(MEM_SIZE_STRINGS[instr.mem_size as usize - 1])?; out.write_str(" ")?; } + if let Some(prefix) = instr.segment_override_for_op(i) { + write!(out, "{}:", prefix)?; + } x.colorize(colors, out)?; if let Some(evex) = instr.prefixes.evex() { if evex.broadcast() && x.is_memory() { diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index e14fb4a..60a18c5 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -4180,7 +4180,7 @@ impl Instruction { Instruction { prefixes: Prefixes::new(0), opcode: Opcode::Invalid, - mem_size: 1, + mem_size: 0, modrm_rrr: RegSpec::rax(), modrm_mmm: RegSpec::rax(), // doubles as sib_base sib_index: RegSpec::rax(), @@ -4954,7 +4954,6 @@ enum OperandCode { // Edq_Gdq = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().operand_case(49).bits(), Gdq_Ev = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().operand_case(40).bits(), Mdq_Gdq = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().operand_case(51).bits(), - G_E_mm_Ib = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().with_imm(false, 0).reg_mem().operand_case(29).bits(), G_E_xmm_Ib = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().operand_case(22).bits(), G_E_xmm_Ub = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().operand_case(60).bits(), G_U_xmm_Ub = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().operand_case(61).bits(), @@ -4971,7 +4970,7 @@ enum OperandCode { Gv_M = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().only_modrm_operands().reg_mem().operand_case(25).bits(), MOVDIR64B = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(108).bits(), M_Gv = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(109).bits(), - Gb_Eb_Ib = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().with_imm(false, 0).byte_operands().reg_mem().operand_case(40).bits(), + Gv_Ev_Ib = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().with_imm(false, 0).reg_mem().operand_case(40).bits(), Gv_Ev_Iv = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(41).bits(), Rv_Gmm_Ib = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_modrm().read_E().reg_mem().operand_case(55).bits(), // gap, 0x9a @@ -4984,11 +4983,13 @@ enum OperandCode { Gd_U_xmm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(59).bits(), Gv_E_xmm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(60).bits(), //= 0x816f, // mirror G_xmm_Edq, but also read an immediate - G_xmm_Ed_Ib = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(61).bits(), + G_xmm_Ew_Ib = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(61).bits(), G_U_xmm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(62).bits(), G_M_xmm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(20).bits(), G_E_xmm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(21).bits(), E_G_xmm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().mem_reg().operand_case(19).bits(), + G_Ed_xmm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(31).bits(), + Ed_G_xmm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().mem_reg().operand_case(29).bits(), M_G_xmm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().mem_reg().operand_case(63).bits(), G_E_mm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(64).bits(), G_U_mm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(65).bits(), @@ -5000,7 +5001,7 @@ enum OperandCode { Ev_Gv_Ib = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(71).bits(), Ev_Gv_CL = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(72).bits(), G_mm_U_mm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(73).bits(), - G_Md_mm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(74).bits(), + G_Mq_mm = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().read_E().reg_mem().operand_case(74).bits(), G_mm_Ew_Ib = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().operand_case(75).bits(), G_E_q = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().operand_case(76).bits(), E_G_q = OperandCodeBuilder::new().op0_is_rrr_and_embedded_instructions().operand_case(77).bits(), @@ -5029,6 +5030,11 @@ enum OperandCode { Yb_AL = OperandCodeBuilder::new().special_case(99).bits(), Yb_Xb = OperandCodeBuilder::new().special_case(100).bits(), Yv_AX = OperandCodeBuilder::new().special_case(101).bits(), + INV_Gv_M = OperandCodeBuilder::new().special_case(102).bits(), + PMOVX_G_E_xmm = OperandCodeBuilder::new().operand_case(103).bits(), + PMOVX_E_G_xmm = OperandCodeBuilder::new().operand_case(104).bits(), + G_Ev_xmm_Ib = OperandCodeBuilder::new().operand_case(105).bits(), + G_E_mm_Ib = OperandCodeBuilder::new().operand_case(106).bits(), } const LOCKABLE_INSTRUCTIONS: &[Opcode] = &[ @@ -5205,7 +5211,7 @@ const OPCODES: [OpcodeRecord; 256] = [ OpcodeRecord(Interpretation::Instruction(Opcode::PUSH), OperandCode::Ivs), OpcodeRecord(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev_Iv), OpcodeRecord(Interpretation::Instruction(Opcode::PUSH), OperandCode::Ibs), - OpcodeRecord(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gb_Eb_Ib), + OpcodeRecord(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev_Ib), OpcodeRecord(Interpretation::Instruction(Opcode::INS), OperandCode::Yb_DX), OpcodeRecord(Interpretation::Instruction(Opcode::INS), OperandCode::Yv_DX), OpcodeRecord(Interpretation::Instruction(Opcode::OUTS), OperandCode::DX_Xb), @@ -5640,9 +5646,9 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x0e => OpcodeRecord(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), 0x0f => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), - 0x10 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSD), OperandCode::G_E_xmm), - 0x11 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSD), OperandCode::E_G_xmm), - 0x12 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVDDUP), OperandCode::G_E_xmm), + 0x10 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSD), OperandCode::PMOVX_G_E_xmm), + 0x11 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSD), OperandCode::PMOVX_E_G_xmm), + 0x12 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVDDUP), OperandCode::PMOVX_G_E_xmm), 0x13 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x14 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x15 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), @@ -5669,8 +5675,8 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x29 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x2a => OpcodeRecord(Interpretation::Instruction(Opcode::CVTSI2SD), OperandCode::G_xmm_Edq), 0x2b => OpcodeRecord(Interpretation::Instruction(Opcode::MOVNTSD), OperandCode::M_G_xmm), - 0x2c => OpcodeRecord(Interpretation::Instruction(Opcode::CVTTSD2SI), OperandCode::G_E_xmm), - 0x2d => OpcodeRecord(Interpretation::Instruction(Opcode::CVTSD2SI), OperandCode::G_E_xmm), + 0x2c => OpcodeRecord(Interpretation::Instruction(Opcode::CVTTSD2SI), OperandCode::PMOVX_G_E_xmm), + 0x2d => OpcodeRecord(Interpretation::Instruction(Opcode::CVTSD2SI), OperandCode::PMOVX_G_E_xmm), 0x2e => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x2f => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), @@ -5709,21 +5715,21 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x4f => OpcodeRecord(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), 0x50 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - 0x51 => OpcodeRecord(Interpretation::Instruction(Opcode::SQRTSD), OperandCode::G_E_xmm), + 0x51 => OpcodeRecord(Interpretation::Instruction(Opcode::SQRTSD), OperandCode::PMOVX_G_E_xmm), 0x52 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x53 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x54 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x55 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x56 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x57 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - 0x58 => OpcodeRecord(Interpretation::Instruction(Opcode::ADDSD), OperandCode::G_E_xmm), - 0x59 => OpcodeRecord(Interpretation::Instruction(Opcode::MULSD), OperandCode::G_E_xmm), - 0x5a => OpcodeRecord(Interpretation::Instruction(Opcode::CVTSD2SS), OperandCode::G_E_xmm), + 0x58 => OpcodeRecord(Interpretation::Instruction(Opcode::ADDSD), OperandCode::PMOVX_G_E_xmm), + 0x59 => OpcodeRecord(Interpretation::Instruction(Opcode::MULSD), OperandCode::PMOVX_G_E_xmm), + 0x5a => OpcodeRecord(Interpretation::Instruction(Opcode::CVTSD2SS), OperandCode::PMOVX_G_E_xmm), 0x5b => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - 0x5c => OpcodeRecord(Interpretation::Instruction(Opcode::SUBSD), OperandCode::G_E_xmm), - 0x5d => OpcodeRecord(Interpretation::Instruction(Opcode::MINSD), OperandCode::G_E_xmm), - 0x5e => OpcodeRecord(Interpretation::Instruction(Opcode::DIVSD), OperandCode::G_E_xmm), - 0x5f => OpcodeRecord(Interpretation::Instruction(Opcode::MAXSD), OperandCode::G_E_xmm), + 0x5c => OpcodeRecord(Interpretation::Instruction(Opcode::SUBSD), OperandCode::PMOVX_G_E_xmm), + 0x5d => OpcodeRecord(Interpretation::Instruction(Opcode::MINSD), OperandCode::PMOVX_G_E_xmm), + 0x5e => OpcodeRecord(Interpretation::Instruction(Opcode::DIVSD), OperandCode::PMOVX_G_E_xmm), + 0x5f => OpcodeRecord(Interpretation::Instruction(Opcode::MAXSD), OperandCode::PMOVX_G_E_xmm), 0x60 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x61 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), @@ -5815,10 +5821,10 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { // 0xb0 0xb0 => OpcodeRecord(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), 0xb1 => OpcodeRecord(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), - 0xb2 => OpcodeRecord(Interpretation::Instruction(Opcode::LSS), OperandCode::Gv_M), + 0xb2 => OpcodeRecord(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), 0xb3 => OpcodeRecord(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), - 0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::Gv_M), - 0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::Gv_M), + 0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), + 0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), 0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_b), OperandCode::Gv_Eb), 0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_w), OperandCode::Gv_Ew), 0xb8 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), @@ -5917,8 +5923,8 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x0e => OpcodeRecord(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), 0x0f => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), - 0x10 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSS), OperandCode::G_E_xmm), - 0x11 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSS), OperandCode::E_G_xmm), + 0x10 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSS), OperandCode::G_Ed_xmm), + 0x11 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSS), OperandCode::Ed_G_xmm), 0x12 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVSLDUP), OperandCode::G_E_xmm), 0x13 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x14 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), @@ -5986,21 +5992,21 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x4f => OpcodeRecord(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), // 0x50 0x50 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - 0x51 => OpcodeRecord(Interpretation::Instruction(Opcode::SQRTSS), OperandCode::G_E_xmm), - 0x52 => OpcodeRecord(Interpretation::Instruction(Opcode::RSQRTSS), OperandCode::G_E_xmm), - 0x53 => OpcodeRecord(Interpretation::Instruction(Opcode::RCPSS), OperandCode::G_E_xmm), + 0x51 => OpcodeRecord(Interpretation::Instruction(Opcode::SQRTSS), OperandCode::G_Ed_xmm), + 0x52 => OpcodeRecord(Interpretation::Instruction(Opcode::RSQRTSS), OperandCode::G_Ed_xmm), + 0x53 => OpcodeRecord(Interpretation::Instruction(Opcode::RCPSS), OperandCode::G_Ed_xmm), 0x54 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x55 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x56 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x57 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - 0x58 => OpcodeRecord(Interpretation::Instruction(Opcode::ADDSS), OperandCode::G_E_xmm), - 0x59 => OpcodeRecord(Interpretation::Instruction(Opcode::MULSS), OperandCode::G_E_xmm), - 0x5a => OpcodeRecord(Interpretation::Instruction(Opcode::CVTSS2SD), OperandCode::G_E_xmm), + 0x58 => OpcodeRecord(Interpretation::Instruction(Opcode::ADDSS), OperandCode::G_Ed_xmm), + 0x59 => OpcodeRecord(Interpretation::Instruction(Opcode::MULSS), OperandCode::G_Ed_xmm), + 0x5a => OpcodeRecord(Interpretation::Instruction(Opcode::CVTSS2SD), OperandCode::PMOVX_G_E_xmm), 0x5b => OpcodeRecord(Interpretation::Instruction(Opcode::CVTTPS2DQ), OperandCode::G_E_xmm), - 0x5c => OpcodeRecord(Interpretation::Instruction(Opcode::SUBSS), OperandCode::G_E_xmm), - 0x5d => OpcodeRecord(Interpretation::Instruction(Opcode::MINSS), OperandCode::G_E_xmm), - 0x5e => OpcodeRecord(Interpretation::Instruction(Opcode::DIVSS), OperandCode::G_E_xmm), - 0x5f => OpcodeRecord(Interpretation::Instruction(Opcode::MAXSS), OperandCode::G_E_xmm), + 0x5c => OpcodeRecord(Interpretation::Instruction(Opcode::SUBSS), OperandCode::G_Ed_xmm), + 0x5d => OpcodeRecord(Interpretation::Instruction(Opcode::MINSS), OperandCode::G_Ed_xmm), + 0x5e => OpcodeRecord(Interpretation::Instruction(Opcode::DIVSS), OperandCode::G_Ed_xmm), + 0x5f => OpcodeRecord(Interpretation::Instruction(Opcode::MAXSS), OperandCode::G_Ed_xmm), // 0x60 0x60 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), 0x61 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), @@ -6092,10 +6098,10 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { // 0xb0 0xb0 => OpcodeRecord(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), 0xb1 => OpcodeRecord(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), - 0xb2 => OpcodeRecord(Interpretation::Instruction(Opcode::LSS), OperandCode::Gv_M), + 0xb2 => OpcodeRecord(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), 0xb3 => OpcodeRecord(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), - 0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::Gv_M), - 0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::Gv_M), + 0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), + 0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), 0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_b), OperandCode::Gv_Eb), 0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_w), OperandCode::Gv_Ew), 0xb8 => OpcodeRecord(Interpretation::Instruction(Opcode::POPCNT), OperandCode::Gv_Ev), @@ -6196,12 +6202,12 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x10 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVUPD), OperandCode::G_E_xmm), 0x11 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVUPD), OperandCode::E_G_xmm), - 0x12 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVLPD), OperandCode::G_M_xmm), - 0x13 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVLPD), OperandCode::M_G_xmm), + 0x12 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVLPD), OperandCode::PMOVX_G_E_xmm), + 0x13 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVLPD), OperandCode::PMOVX_E_G_xmm), 0x14 => OpcodeRecord(Interpretation::Instruction(Opcode::UNPCKLPD), OperandCode::G_E_xmm), 0x15 => OpcodeRecord(Interpretation::Instruction(Opcode::UNPCKHPD), OperandCode::G_E_xmm), - 0x16 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVHPD), OperandCode::G_M_xmm), - 0x17 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVHPD), OperandCode::M_G_xmm), + 0x16 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVHPD), OperandCode::PMOVX_G_E_xmm), + 0x17 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVHPD), OperandCode::PMOVX_E_G_xmm), 0x18 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), 0x19 => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), 0x1a => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), @@ -6225,8 +6231,8 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x2b => OpcodeRecord(Interpretation::Instruction(Opcode::MOVNTPD), OperandCode::M_G_xmm), 0x2c => OpcodeRecord(Interpretation::Instruction(Opcode::CVTTPD2PI), OperandCode::G_mm_E_xmm), 0x2d => OpcodeRecord(Interpretation::Instruction(Opcode::CVTPD2PI), OperandCode::G_mm_E_xmm), - 0x2e => OpcodeRecord(Interpretation::Instruction(Opcode::UCOMISD), OperandCode::G_E_xmm), - 0x2f => OpcodeRecord(Interpretation::Instruction(Opcode::COMISD), OperandCode::G_E_xmm), + 0x2e => OpcodeRecord(Interpretation::Instruction(Opcode::UCOMISD), OperandCode::PMOVX_G_E_xmm), + 0x2f => OpcodeRecord(Interpretation::Instruction(Opcode::COMISD), OperandCode::PMOVX_G_E_xmm), 0x30 => OpcodeRecord(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), 0x31 => OpcodeRecord(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), @@ -6366,10 +6372,10 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { // 0xb0 0xb0 => OpcodeRecord(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), 0xb1 => OpcodeRecord(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), - 0xb2 => OpcodeRecord(Interpretation::Instruction(Opcode::LSS), OperandCode::Gv_M), + 0xb2 => OpcodeRecord(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), 0xb3 => OpcodeRecord(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), - 0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::Gv_M), - 0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::Gv_M), + 0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), + 0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), 0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_b), OperandCode::Gv_Eb), 0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_w), OperandCode::Gv_Ew), 0xb8 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), @@ -6385,7 +6391,7 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0xc1 => OpcodeRecord(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), 0xc2 => OpcodeRecord(Interpretation::Instruction(Opcode::CMPPD), OperandCode::G_E_xmm_Ib), 0xc3 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - 0xc4 => OpcodeRecord(Interpretation::Instruction(Opcode::PINSRW), OperandCode::G_xmm_Ed_Ib), + 0xc4 => OpcodeRecord(Interpretation::Instruction(Opcode::PINSRW), OperandCode::G_xmm_Ew_Ib), 0xc5 => OpcodeRecord(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::G_U_xmm_Ub), 0xc6 => OpcodeRecord(Interpretation::Instruction(Opcode::SHUFPD), OperandCode::G_E_xmm_Ib), 0xc7 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), @@ -6404,7 +6410,7 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0xd3 => OpcodeRecord(Interpretation::Instruction(Opcode::PSRLQ), OperandCode::G_E_xmm), 0xd4 => OpcodeRecord(Interpretation::Instruction(Opcode::PADDQ), OperandCode::G_E_xmm), 0xd5 => OpcodeRecord(Interpretation::Instruction(Opcode::PMULLW), OperandCode::G_E_xmm), - 0xd6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVQ), OperandCode::E_G_xmm), + 0xd6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVQ), OperandCode::PMOVX_E_G_xmm), 0xd7 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVMSKB), OperandCode::Gd_U_xmm), 0xd8 => OpcodeRecord(Interpretation::Instruction(Opcode::PSUBUSB), OperandCode::G_E_xmm), 0xd9 => OpcodeRecord(Interpretation::Instruction(Opcode::PSUBUSW), OperandCode::G_E_xmm), @@ -6475,7 +6481,7 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x14 => OpcodeRecord(Interpretation::Instruction(Opcode::UNPCKLPS), OperandCode::G_E_xmm), 0x15 => OpcodeRecord(Interpretation::Instruction(Opcode::UNPCKHPS), OperandCode::G_E_xmm), 0x16 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f16), - 0x17 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVHPS), OperandCode::M_G_xmm), + 0x17 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVHPS), OperandCode::PMOVX_E_G_xmm), 0x18 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), 0x19 => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), 0x1a => OpcodeRecord(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), @@ -6499,8 +6505,8 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x2b => OpcodeRecord(Interpretation::Instruction(Opcode::MOVNTPS), OperandCode::M_G_xmm), 0x2c => OpcodeRecord(Interpretation::Instruction(Opcode::CVTTPS2PI), OperandCode::G_mm_E_xmm), 0x2d => OpcodeRecord(Interpretation::Instruction(Opcode::CVTPS2PI), OperandCode::G_mm_E_xmm), - 0x2e => OpcodeRecord(Interpretation::Instruction(Opcode::UCOMISS), OperandCode::G_E_xmm), - 0x2f => OpcodeRecord(Interpretation::Instruction(Opcode::COMISS), OperandCode::G_E_xmm), + 0x2e => OpcodeRecord(Interpretation::Instruction(Opcode::UCOMISS), OperandCode::PMOVX_G_E_xmm), + 0x2f => OpcodeRecord(Interpretation::Instruction(Opcode::COMISS), OperandCode::PMOVX_G_E_xmm), // 0x30 0x30 => OpcodeRecord(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), 0x31 => OpcodeRecord(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), @@ -6548,7 +6554,7 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x57 => OpcodeRecord(Interpretation::Instruction(Opcode::XORPS), OperandCode::G_E_xmm), 0x58 => OpcodeRecord(Interpretation::Instruction(Opcode::ADDPS), OperandCode::G_E_xmm), 0x59 => OpcodeRecord(Interpretation::Instruction(Opcode::MULPS), OperandCode::G_E_xmm), - 0x5a => OpcodeRecord(Interpretation::Instruction(Opcode::CVTPS2PD), OperandCode::G_E_xmm), + 0x5a => OpcodeRecord(Interpretation::Instruction(Opcode::CVTPS2PD), OperandCode::PMOVX_G_E_xmm), 0x5b => OpcodeRecord(Interpretation::Instruction(Opcode::CVTDQ2PS), OperandCode::G_E_xmm), 0x5c => OpcodeRecord(Interpretation::Instruction(Opcode::SUBPS), OperandCode::G_E_xmm), 0x5d => OpcodeRecord(Interpretation::Instruction(Opcode::MINPS), OperandCode::G_E_xmm), @@ -6648,10 +6654,10 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { // 0xb0 0xb0 => OpcodeRecord(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), 0xb1 => OpcodeRecord(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), - 0xb2 => OpcodeRecord(Interpretation::Instruction(Opcode::LSS), OperandCode::Gv_M), + 0xb2 => OpcodeRecord(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), 0xb3 => OpcodeRecord(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), - 0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::Gv_M), - 0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::Gv_M), + 0xb4 => OpcodeRecord(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), + 0xb5 => OpcodeRecord(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), 0xb6 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_b), OperandCode::Gv_Eb), 0xb7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVZX_w), OperandCode::Gv_Ew), 0xb8 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // JMPE, ITANIUM @@ -6707,7 +6713,7 @@ fn read_0f_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0xe4 => OpcodeRecord(Interpretation::Instruction(Opcode::PMULHUW), OperandCode::G_E_mm), 0xe5 => OpcodeRecord(Interpretation::Instruction(Opcode::PMULHW), OperandCode::G_E_mm), 0xe6 => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), - 0xe7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVNTQ), OperandCode::G_Md_mm), + 0xe7 => OpcodeRecord(Interpretation::Instruction(Opcode::MOVNTQ), OperandCode::G_Mq_mm), 0xe8 => OpcodeRecord(Interpretation::Instruction(Opcode::PSUBSB), OperandCode::G_E_mm), 0xe9 => OpcodeRecord(Interpretation::Instruction(Opcode::PSUBSW), OperandCode::G_E_mm), 0xea => OpcodeRecord(Interpretation::Instruction(Opcode::PMINSW), OperandCode::G_E_mm), @@ -6748,7 +6754,7 @@ fn read_0f38_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0xf6 => OpcodeRecord(Interpretation::Instruction(Opcode::ADOX), OperandCode::Gv_Ev), 0xf8 => { prefixes.unset_operand_size(); - OpcodeRecord(Interpretation::Instruction(Opcode::ENQCMDS), OperandCode::Gv_M) + OpcodeRecord(Interpretation::Instruction(Opcode::ENQCMDS), OperandCode::INV_Gv_M) }, 0xfa => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38fa), 0xfb => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38fb), @@ -6762,7 +6768,7 @@ fn read_0f38_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0xf1 => OpcodeRecord(Interpretation::Instruction(Opcode::CRC32), OperandCode::Gdq_Ev), 0xf8 => { prefixes.unset_operand_size(); - OpcodeRecord(Interpretation::Instruction(Opcode::ENQCMD), OperandCode::Gv_M) + OpcodeRecord(Interpretation::Instruction(Opcode::ENQCMD), OperandCode::INV_Gv_M) }, _ => OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; @@ -6794,22 +6800,22 @@ fn read_0f38_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x1c => OpcodeRecord(Interpretation::Instruction(Opcode::PABSB), OperandCode::G_E_xmm), 0x1d => OpcodeRecord(Interpretation::Instruction(Opcode::PABSW), OperandCode::G_E_xmm), 0x1e => OpcodeRecord(Interpretation::Instruction(Opcode::PABSD), OperandCode::G_E_xmm), - 0x20 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXBW), OperandCode::G_E_xmm), - 0x21 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXBD), OperandCode::G_E_xmm), - 0x22 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXBQ), OperandCode::G_E_xmm), - 0x23 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXWD), OperandCode::G_E_xmm), - 0x24 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXWQ), OperandCode::G_E_xmm), - 0x25 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXDQ), OperandCode::G_E_xmm), + 0x20 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXBW), OperandCode::PMOVX_G_E_xmm), + 0x21 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXBD), OperandCode::PMOVX_G_E_xmm), + 0x22 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXBQ), OperandCode::PMOVX_G_E_xmm), + 0x23 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXWD), OperandCode::PMOVX_G_E_xmm), + 0x24 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXWQ), OperandCode::PMOVX_G_E_xmm), + 0x25 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVSXDQ), OperandCode::PMOVX_G_E_xmm), 0x28 => OpcodeRecord(Interpretation::Instruction(Opcode::PMULDQ), OperandCode::G_E_xmm), 0x29 => OpcodeRecord(Interpretation::Instruction(Opcode::PCMPEQQ), OperandCode::G_E_xmm), 0x2a => OpcodeRecord(Interpretation::Instruction(Opcode::MOVNTDQA), OperandCode::G_M_xmm), 0x2b => OpcodeRecord(Interpretation::Instruction(Opcode::PACKUSDW), OperandCode::G_E_xmm), - 0x30 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXBW), OperandCode::G_E_xmm), - 0x31 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXBD), OperandCode::G_E_xmm), - 0x32 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXBQ), OperandCode::G_E_xmm), - 0x33 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXWD), OperandCode::G_E_xmm), - 0x34 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXWQ), OperandCode::G_E_xmm), - 0x35 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXDQ), OperandCode::G_E_xmm), + 0x30 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXBW), OperandCode::PMOVX_G_E_xmm), + 0x31 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXBD), OperandCode::PMOVX_G_E_xmm), + 0x32 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXBQ), OperandCode::PMOVX_G_E_xmm), + 0x33 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXWD), OperandCode::PMOVX_G_E_xmm), + 0x34 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXWQ), OperandCode::PMOVX_G_E_xmm), + 0x35 => OpcodeRecord(Interpretation::Instruction(Opcode::PMOVZXDQ), OperandCode::PMOVX_G_E_xmm), 0x37 => OpcodeRecord(Interpretation::Instruction(Opcode::PCMPGTQ), OperandCode::G_E_xmm), 0x38 => OpcodeRecord(Interpretation::Instruction(Opcode::PMINSB), OperandCode::G_E_xmm), 0x39 => OpcodeRecord(Interpretation::Instruction(Opcode::PMINSD), OperandCode::G_E_xmm), @@ -6821,9 +6827,9 @@ fn read_0f38_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x3f => OpcodeRecord(Interpretation::Instruction(Opcode::PMAXUD), OperandCode::G_E_xmm), 0x40 => OpcodeRecord(Interpretation::Instruction(Opcode::PMULLD), OperandCode::G_E_xmm), 0x41 => OpcodeRecord(Interpretation::Instruction(Opcode::PHMINPOSUW), OperandCode::G_E_xmm), - 0x80 => OpcodeRecord(Interpretation::Instruction(Opcode::INVEPT), OperandCode::Gv_M), - 0x81 => OpcodeRecord(Interpretation::Instruction(Opcode::INVVPID), OperandCode::Gv_M), - 0x82 => OpcodeRecord(Interpretation::Instruction(Opcode::INVPCID), OperandCode::Gv_M), + 0x80 => OpcodeRecord(Interpretation::Instruction(Opcode::INVEPT), OperandCode::INV_Gv_M), + 0x81 => OpcodeRecord(Interpretation::Instruction(Opcode::INVVPID), OperandCode::INV_Gv_M), + 0x82 => OpcodeRecord(Interpretation::Instruction(Opcode::INVPCID), OperandCode::INV_Gv_M), 0xcf => OpcodeRecord(Interpretation::Instruction(Opcode::GF2P8MULB), OperandCode::G_E_xmm), 0xdb => OpcodeRecord(Interpretation::Instruction(Opcode::AESIMC), OperandCode::G_E_xmm), 0xdc => OpcodeRecord(Interpretation::Instruction(Opcode::AESENC), OperandCode::G_E_xmm), @@ -6876,9 +6882,9 @@ fn read_0f3a_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { if prefixes.operand_size() { if opcode == 0x16 && prefixes.rex().w() { - return OpcodeRecord(Interpretation::Instruction(Opcode::PEXTRQ), OperandCode::G_E_xmm_Ib); + return OpcodeRecord(Interpretation::Instruction(Opcode::PEXTRQ), OperandCode::G_Ev_xmm_Ib); } else if opcode == 0x22 && prefixes.rex().w() { - return OpcodeRecord(Interpretation::Instruction(Opcode::PINSRQ), OperandCode::G_E_xmm_Ib); + return OpcodeRecord(Interpretation::Instruction(Opcode::PINSRQ), OperandCode::G_Ev_xmm_Ib); } return match opcode { @@ -6890,13 +6896,13 @@ fn read_0f3a_opcode(opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { 0x0d => OpcodeRecord(Interpretation::Instruction(Opcode::BLENDPD), OperandCode::G_E_xmm_Ib), 0x0e => OpcodeRecord(Interpretation::Instruction(Opcode::PBLENDW), OperandCode::G_E_xmm_Ib), 0x0f => OpcodeRecord(Interpretation::Instruction(Opcode::PALIGNR), OperandCode::G_E_xmm_Ib), - 0x14 => OpcodeRecord(Interpretation::Instruction(Opcode::PEXTRB), OperandCode::G_E_xmm_Ib), - 0x15 => OpcodeRecord(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::G_E_xmm_Ib), - 0x16 => OpcodeRecord(Interpretation::Instruction(Opcode::PEXTRD), OperandCode::G_E_xmm_Ib), - 0x17 => OpcodeRecord(Interpretation::Instruction(Opcode::EXTRACTPS), OperandCode::G_E_xmm_Ib), - 0x20 => OpcodeRecord(Interpretation::Instruction(Opcode::PINSRB), OperandCode::G_E_xmm_Ib), - 0x21 => OpcodeRecord(Interpretation::Instruction(Opcode::INSERTPS), OperandCode::G_E_xmm_Ib), - 0x22 => OpcodeRecord(Interpretation::Instruction(Opcode::PINSRD), OperandCode::G_E_xmm_Ib), + 0x14 => OpcodeRecord(Interpretation::Instruction(Opcode::PEXTRB), OperandCode::G_Ev_xmm_Ib), + 0x15 => OpcodeRecord(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::G_Ev_xmm_Ib), + 0x16 => OpcodeRecord(Interpretation::Instruction(Opcode::PEXTRD), OperandCode::G_Ev_xmm_Ib), + 0x17 => OpcodeRecord(Interpretation::Instruction(Opcode::EXTRACTPS), OperandCode::G_Ev_xmm_Ib), + 0x20 => OpcodeRecord(Interpretation::Instruction(Opcode::PINSRB), OperandCode::G_Ev_xmm_Ib), + 0x21 => OpcodeRecord(Interpretation::Instruction(Opcode::INSERTPS), OperandCode::G_Ev_xmm_Ib), + 0x22 => OpcodeRecord(Interpretation::Instruction(Opcode::PINSRD), OperandCode::G_Ev_xmm_Ib), 0x40 => OpcodeRecord(Interpretation::Instruction(Opcode::DPPS), OperandCode::G_E_xmm_Ib), 0x41 => OpcodeRecord(Interpretation::Instruction(Opcode::DPPD), OperandCode::G_E_xmm_Ib), 0x42 => OpcodeRecord(Interpretation::Instruction(Opcode::MPSADBW), OperandCode::G_E_xmm_Ib), @@ -7423,6 +7429,12 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, } else if opcode == Opcode::CALLF || opcode == Opcode::JMPF { return Err(DecodeError::InvalidOperand); } + } else { + if opcode == Opcode::CALL || opcode == Opcode::JMP || opcode == Opcode::PUSH || opcode == Opcode::POP { + instruction.mem_size = 8; + } else if opcode == Opcode::CALLF || opcode == Opcode::JMPF { + instruction.mem_size = 9; + } } instruction.opcode = opcode; instruction.operand_count = 1; @@ -7432,8 +7444,14 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, let modrm = read_modrm(&mut bytes_iter, length)?; instruction.operands[1] = read_E(&mut bytes_iter, instruction, modrm, 1, length)?; + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 1; + } instruction.modrm_rrr = RegSpec::gp_from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), opwidth, instruction.prefixes.rex().present()); + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 1; + } instruction.operand_count = 2; }, 16 => { @@ -7443,6 +7461,9 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, instruction.operands[1] = read_E(&mut bytes_iter, instruction, modrm, 2, length)?; instruction.modrm_rrr = RegSpec::gp_from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), opwidth, instruction.prefixes.rex().present()); + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 2; + } instruction.operand_count = 2; }, 17 => { @@ -7450,6 +7471,7 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, let modrm = read_modrm(&mut bytes_iter, length)?; instruction.operands[1] = read_E(&mut bytes_iter, instruction, modrm, 4 /* opwidth */, length)?; + instruction.mem_size = 4; instruction.modrm_rrr = RegSpec::gp_from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), opwidth, instruction.prefixes.rex().present()); instruction.operand_count = 2; @@ -7466,6 +7488,8 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, if instruction.operands[0] == OperandSpec::RegMMM { // fix the register to XMM instruction.modrm_mmm.bank = RegisterBank::X; + } else { + instruction.mem_size = 16; } }, op @ 20 | @@ -7480,6 +7504,12 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, // fix the register to XMM instruction.modrm_mmm.bank = RegisterBank::X; } + } else { + if instruction.opcode == Opcode::MOVDDUP { + instruction.mem_size = 8; + } else { + instruction.mem_size = 16; + } } }, 22 => { @@ -7491,6 +7521,15 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, instruction.imm = read_num(&mut bytes_iter, 1)? as u8 as u64; *length += 1; + if instruction.operands[1] != OperandSpec::RegMMM { + if instruction.opcode == Opcode::CMPSS { + instruction.mem_size = 4; + } else if instruction.opcode == Opcode::CMPSD { + instruction.mem_size = 8; + } else { + instruction.mem_size = 16; + } + } instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; }, @@ -7544,12 +7583,16 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, return Ok(()); }, 29 => { - instruction.modrm_rrr = RegSpec { bank: RegisterBank::MM, num: (modrm >> 3) & 7 }; - if instruction.operands[1] == OperandSpec::RegMMM { - instruction.modrm_mmm.bank = RegisterBank::MM; + instruction.modrm_rrr.bank = RegisterBank::X; + instruction.operands[0] = mem_oper; + instruction.operands[1] = OperandSpec::RegRRR; + instruction.operand_count = 2; + if instruction.operands[0] == OperandSpec::RegMMM { + // fix the register to XMM + instruction.modrm_mmm.bank = RegisterBank::X; + } else { + instruction.mem_size = 4; } - instruction.operands[2] = OperandSpec::ImmI8; - instruction.operand_count = 3; }, 30 => { instruction.operands[0] = mem_oper; @@ -7560,8 +7603,26 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, instruction.opcode = [ Opcode::POP, ][r as usize]; + if mem_oper != OperandSpec::RegMMM { + // the right size is set by default except for the default case; by default + // operands are dword, but 0x8f `pop` defaults to qword (with no way to encode a + // `pop dword [mem]`) + if !instruction.prefixes.operand_size() { + instruction.mem_size = 8; + } + } instruction.operand_count = 1; } + 31 => { + instruction.modrm_rrr.bank = RegisterBank::X; + instruction.operand_count = 2; + if instruction.operands[1] == OperandSpec::RegMMM { + // fix the register to XMM + instruction.modrm_mmm.bank = RegisterBank::X; + } else { + instruction.mem_size = 4; + } + }, _ => { let operand_code: OperandCode = unsafe { core::mem::transmute(operand_code.bits()) }; unlikely_operands(decoder, bytes_iter, instruction, operand_code, mem_oper, length)?; @@ -7573,6 +7634,108 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, } fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, instruction: &mut Instruction, operand_code: OperandCode, mem_oper: OperandSpec, length: &mut u8) -> Result<(), DecodeError> { match operand_code { + OperandCode::G_E_mm_Ib => { + let modrm = read_modrm(&mut bytes_iter, length)?; + + instruction.operands[1] = read_E_mm(&mut bytes_iter, instruction, modrm, length)?; + instruction.modrm_rrr = + RegSpec::from_parts((modrm >> 3) & 7, false, RegisterBank::MM); + instruction.imm = + read_num(&mut bytes_iter, 1)? as u8 as u64; + *length += 1; + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 8; + } + instruction.operands[2] = OperandSpec::ImmI8; + instruction.operand_count = 3; + } + OperandCode::G_Ev_xmm_Ib => { + let modrm = read_modrm(&mut bytes_iter, length)?; + + instruction.operands[1] = read_E_xmm(&mut bytes_iter, instruction, modrm, length)?; + instruction.modrm_rrr = + RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), RegisterBank::X); + instruction.imm = + read_num(&mut bytes_iter, 1)? as u8 as u64; + *length += 1; + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = match instruction.opcode { + Opcode::PEXTRB => 1, + Opcode::PEXTRW => 2, + Opcode::PEXTRD => 4, + Opcode::EXTRACTPS => 4, + Opcode::INSERTPS => 4, + Opcode::PINSRB => 1, + Opcode::PINSRW => 2, + Opcode::PINSRD => 4, + _ => 8, + }; + } + instruction.operands[2] = OperandSpec::ImmI8; + instruction.operand_count = 3; + } + OperandCode::PMOVX_E_G_xmm => { + let modrm = read_modrm(&mut bytes_iter, length)?; + + instruction.modrm_rrr = + RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), RegisterBank::X); + instruction.operands[1] = OperandSpec::RegRRR; + instruction.operands[0] = read_E_xmm(&mut bytes_iter, instruction, modrm, length)?; + if instruction.operands[0] != OperandSpec::RegMMM { + if [].contains(&instruction.opcode) { + instruction.mem_size = 2; + } else { + instruction.mem_size = 8; + } + } else { + if instruction.opcode == Opcode::MOVLPD || instruction.opcode == Opcode::MOVHPD || instruction.opcode == Opcode::MOVHPS { + return Err(DecodeError::InvalidOperand); + } + } + } + OperandCode::PMOVX_G_E_xmm => { + let modrm = read_modrm(&mut bytes_iter, length)?; + + instruction.modrm_rrr = + RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), RegisterBank::X); + instruction.operands[0] = OperandSpec::RegRRR; + instruction.operands[1] = read_E_xmm(&mut bytes_iter, instruction, modrm, length)?; + if instruction.operands[1] != OperandSpec::RegMMM { + if [Opcode::PMOVSXBQ, Opcode::PMOVZXBQ].contains(&instruction.opcode) { + instruction.mem_size = 2; + } else if [Opcode::PMOVZXBD, Opcode::UCOMISS, Opcode::COMISS].contains(&instruction.opcode) { + instruction.mem_size = 4; + } else { + instruction.mem_size = 8; + } + } else { + if instruction.opcode == Opcode::MOVLPD || instruction.opcode == Opcode::MOVHPD { + return Err(DecodeError::InvalidOperand); + } + } + } + OperandCode::INV_Gv_M => { + let modrm = read_modrm(&mut bytes_iter, length)?; + + instruction.modrm_rrr = + RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), RegisterBank::Q); + instruction.operands[0] = OperandSpec::RegRRR; + instruction.operands[1] = read_M(&mut bytes_iter, instruction, modrm, length)?; + if instruction.operands[1] == OperandSpec::RegMMM { + return Err(DecodeError::InvalidOperand); + } + if [Opcode::LFS, Opcode::LGS, Opcode::LSS].contains(&instruction.opcode) { + if instruction.prefixes.rex().w() { + instruction.mem_size = 10; + } else { + instruction.mem_size = 4; + } + } else if [Opcode::ENQCMD, Opcode::ENQCMDS].contains(&instruction.opcode) { + instruction.mem_size = 64; + } else { + instruction.mem_size = 16; + } + } OperandCode::G_U_xmm_Ub => { let modrm = read_modrm(&mut bytes_iter, length)?; @@ -7647,6 +7810,9 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.imm = read_num(&mut bytes_iter, 1)? as u8 as u64; *length += 1; + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 16; + } instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } @@ -7654,6 +7820,8 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.modrm_rrr.bank = RegisterBank::D; if mem_oper == OperandSpec::RegMMM { instruction.modrm_mmm.bank = RegisterBank::D; + } else { + instruction.mem_size = 4; } instruction.operands[1] = mem_oper; instruction.operand_count = 2; @@ -7692,7 +7860,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.modrm_mmm.bank = RegisterBank::X; instruction.operand_count = 2; }, - OperandCode::Gb_Eb_Ib => { + OperandCode::Gv_Ev_Ib => { instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } @@ -7732,6 +7900,8 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter RegSpec::from_parts((modrm >> 3) & 7, false, RegisterBank::MM); if instruction.operands[1] == OperandSpec::RegMMM { instruction.modrm_mmm.bank = RegisterBank::D; + } else { + instruction.mem_size = 2; } instruction.imm = read_num(&mut bytes_iter, 1)? as u8 as u64; @@ -7745,6 +7915,12 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter if mem_oper == OperandSpec::RegMMM { instruction.modrm_mmm.bank = RegisterBank::MM; instruction.modrm_mmm.num &= 0b111; + } else { + if [Opcode::PACKSSWB, Opcode::PCMPGTB, Opcode::PCMPGTW, Opcode::PCMPGTD, Opcode::PACKUSWB, Opcode::PUNPCKHBW, Opcode::PUNPCKHWD, Opcode::PUNPCKHDQ, Opcode::PACKSSDW, Opcode::PSRLW, Opcode::PMULHW, Opcode::PSHUFB, Opcode::PHADDW, Opcode::PHADDD, Opcode::PHADDSW, Opcode::PMADDUBSW, Opcode::PHSUBW, Opcode::PHSUBD, Opcode::PHSUBSW, Opcode::PSIGNB, Opcode::PSIGNW, Opcode::PSIGND, Opcode::PMULHRSW, Opcode::PABSB, Opcode::PABSW, Opcode::PABSD].contains(&instruction.opcode) { + instruction.mem_size = 8; + } else { + instruction.mem_size = 4; + } } instruction.operand_count = 2; }, @@ -7778,6 +7954,9 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter // `opwidth` can be 2, 4, or 8 here. if opwidth is 2, the first operand is a dword. // if opwidth is 4, both registers are dwords. and if opwidth is 8, both registers are // qword. + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 4; + } let regwidth = if opwidth == 2 { 4 } else { @@ -7798,6 +7977,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter unsafe { unreachable_unchecked() } } }; + instruction.mem_size = opwidth; let addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; let imm = read_num(&mut bytes_iter, addr_width)?; *length += addr_width; @@ -7822,6 +8002,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter unsafe { unreachable_unchecked() } } }; + instruction.mem_size = opwidth; let addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; let imm = read_num(&mut bytes_iter, addr_width)?; *length += addr_width; @@ -7872,6 +8053,8 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, opwidth, length)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); + } else { + instruction.mem_size = opwidth; } instruction.modrm_rrr = RegSpec::gp_from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), opwidth, instruction.prefixes.rex().present()); @@ -7900,6 +8083,9 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.modrm_rrr = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), RegisterBank::Q); instruction.operand_count = 2; + if instruction.operands[0] != OperandSpec::RegMMM { + instruction.mem_size = 8; + } } OperandCode::G_E_q => { if instruction.prefixes.operand_size() { @@ -7913,13 +8099,18 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), RegisterBank::Q); instruction.operands[1] = read_E(&mut bytes_iter, instruction, modrm, 8, length)?; instruction.operand_count = 2; + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 8; + } } - OperandCode::G_Md_mm => { + OperandCode::G_Mq_mm => { instruction.operands[1] = instruction.operands[0]; instruction.operands[0] = mem_oper; instruction.modrm_rrr.bank = RegisterBank::MM; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); + } else { + instruction.mem_size = 8; } instruction.modrm_rrr.num &= 0b111; instruction.operand_count = 2; @@ -7962,6 +8153,9 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } } instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, opwidth, length)?; + if instruction.operands[0] != OperandSpec::RegMMM { + instruction.mem_size = 64; + } instruction.operand_count = 1; } OperandCode::ModRM_0x0f0f => { @@ -7972,6 +8166,9 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.operands[1] = read_E_mm(&mut bytes_iter, instruction, modrm, length)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.modrm_rrr = RegSpec { bank: RegisterBank::MM, num: (modrm >> 3) & 7 }; + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 8; + } let opcode = read_modrm(&mut bytes_iter, length)?; match opcode { @@ -8066,8 +8263,10 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else { if instruction.prefixes.rex().w() { instruction.opcode = Opcode::CMPXCHG16B; + instruction.mem_size = 16; } else { instruction.opcode = Opcode::CMPXCHG8B; + instruction.mem_size = 8; } instruction.operand_count = 1; let opwidth = imm_width_from_prefixes_64(SizeCode::vqp, instruction.prefixes); @@ -8094,8 +8293,10 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else { if instruction.prefixes.rex().w() { instruction.opcode = Opcode::CMPXCHG16B; + instruction.mem_size = 16; } else { instruction.opcode = Opcode::CMPXCHG8B; + instruction.mem_size = 8; } instruction.operand_count = 1; let opwidth = imm_width_from_prefixes_64(SizeCode::vqp, instruction.prefixes); @@ -8112,6 +8313,8 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter // word-form operand: instruction.modrm_mmm = RegSpec { bank: RegisterBank::W, num: instruction.modrm_mmm.num }; instruction.opcode = Opcode::RDRAND; + } else { + instruction.mem_size = 8; } instruction.operand_count = 1; return Ok(()); @@ -8150,8 +8353,10 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else { if instruction.prefixes.rex().w() { instruction.opcode = Opcode::CMPXCHG16B; + instruction.mem_size = 16; } else { instruction.opcode = Opcode::CMPXCHG8B; + instruction.mem_size = 8; } instruction.operand_count = 1; let opwidth = imm_width_from_prefixes_64(SizeCode::vqp, instruction.prefixes); @@ -8166,6 +8371,8 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.opcode = Opcode::SENDUIPI; // and the operand is always a qword register instruction.modrm_mmm.bank = RegisterBank::Q; + } else { + instruction.mem_size = 8; } instruction.operand_count = 1; } @@ -8196,8 +8403,10 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter return Err(DecodeError::InvalidOperand); } else { if instruction.prefixes.rex().w() { + instruction.mem_size = 16; Opcode::CMPXCHG16B } else { + instruction.mem_size = 8; Opcode::CMPXCHG8B } } @@ -8207,6 +8416,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOperand); } else { + instruction.mem_size = 63; if instruction.prefixes.rex().w() { Opcode::XRSTORS64 } else { @@ -8219,6 +8429,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOperand); } else { + instruction.mem_size = 63; if instruction.prefixes.rex().w() { Opcode::XSAVEC64 } else { @@ -8231,6 +8442,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOperand); } else { + instruction.mem_size = 63; if instruction.prefixes.rex().w() { Opcode::XSAVES64 } else { @@ -8242,6 +8454,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter if is_reg { Opcode::RDRAND } else { + instruction.mem_size = 8; Opcode::VMPTRLD } } @@ -8249,6 +8462,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter if is_reg { Opcode::RDSEED } else { + instruction.mem_size = 8; Opcode::VMPTRST } } @@ -8485,6 +8699,8 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter if mem_oper == OperandSpec::RegMMM { instruction.modrm_mmm.bank = RegisterBank::MM; instruction.modrm_mmm.num &= 0b111; + } else { + instruction.mem_size = 8; } } OperandCode::Edq_G_mm => { @@ -8498,6 +8714,12 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else { instruction.modrm_mmm.bank = RegisterBank::D; } + } else { + if instruction.prefixes.rex().w() { + instruction.mem_size = 8; + } else { + instruction.mem_size = 4; + } } } OperandCode::Edq_G_xmm => { @@ -8512,6 +8734,13 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else { instruction.modrm_mmm.bank = RegisterBank::D; } + } else { + if instruction.prefixes.rex().w() { + instruction.opcode = Opcode::MOVQ; + instruction.mem_size = 8; + } else { + instruction.mem_size = 4; + } } } OperandCode::E_G_mm => { @@ -8522,6 +8751,8 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter if mem_oper == OperandSpec::RegMMM { instruction.modrm_mmm.bank = RegisterBank::MM; instruction.modrm_mmm.num &= 0b111; + } else { + instruction.mem_size = 8; } } /* @@ -8543,7 +8774,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } } }, - OperandCode::G_xmm_Ed_Ib => { + OperandCode::G_xmm_Ew_Ib => { instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; instruction.imm = @@ -8552,12 +8783,16 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.modrm_rrr.bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.modrm_mmm.bank = RegisterBank::D; + } else { + instruction.mem_size = 2; } }, OperandCode::G_xmm_Eq => { instruction.modrm_rrr.bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.modrm_mmm.bank = RegisterBank::Q; + } else { + instruction.mem_size = 8; } }, OperandCode::G_mm_E_xmm => { @@ -8565,6 +8800,8 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.modrm_rrr.num &= 0b111; if mem_oper == OperandSpec::RegMMM { instruction.modrm_mmm.bank = RegisterBank::X; + } else { + instruction.mem_size = 16; } }, op @ OperandCode::G_xmm_U_mm | @@ -8576,6 +8813,12 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else { if op == OperandCode::G_xmm_U_mm { return Err(DecodeError::InvalidOperand); + } else { + if instruction.prefixes.rex().w() { + instruction.mem_size = 8; + } else { + instruction.mem_size = 4; + } } } }, @@ -8666,6 +8909,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.modrm_mmm.bank = RegisterBank::X; instruction.opcode = Opcode::MOVHLPS; } else { + instruction.mem_size = 8; if instruction.prefixes.operand_size() { instruction.opcode = Opcode::MOVLPD; } else { @@ -8683,6 +8927,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } instruction.opcode = Opcode::MOVLHPS; } else { + instruction.mem_size = 8; if instruction.prefixes.operand_size() { instruction.opcode = Opcode::MOVHPD; } else { @@ -8706,6 +8951,9 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter _ => Opcode::NOP, } }; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 64; + } } OperandCode::Gd_U_xmm => { if instruction.operands[1] != OperandSpec::RegMMM { @@ -8718,6 +8966,8 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter OperandCode::Gv_E_xmm => { if instruction.operands[1] == OperandSpec::RegMMM { instruction.modrm_mmm.bank = RegisterBank::X; + } else { + instruction.mem_size = 4; } } OperandCode::M_G_xmm => { @@ -8726,6 +8976,14 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter if instruction.operands[0] == OperandSpec::RegMMM { instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOperand); + } else { + if instruction.opcode == Opcode::MOVNTSS { + instruction.mem_size = 4; + } else if instruction.opcode == Opcode::MOVNTPD || instruction.opcode == Opcode::MOVNTDQ || instruction.opcode == Opcode::MOVNTPS { + instruction.mem_size = 16; + } else { + instruction.mem_size = 8; + } } instruction.modrm_rrr.bank = RegisterBank::X; } @@ -8751,6 +9009,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.operands[0] = OperandSpec::RegMMM; } else { instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, opwidth, length)?; + instruction.mem_size = 2; } }, OperandCode::Sw_Ew => { @@ -8784,6 +9043,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.operands[1] = OperandSpec::RegMMM; } else { instruction.operands[1] = read_M(&mut bytes_iter, instruction, modrm, length)?; + instruction.mem_size = 2; } }, OperandCode::CVT_AA => { @@ -8884,6 +9144,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else { instruction.opcode = Opcode::SGDT; instruction.operand_count = 1; + instruction.mem_size = 63; instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, opwidth, length)?; } } else if r == 1 { @@ -8940,6 +9201,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else { instruction.opcode = Opcode::SIDT; instruction.operand_count = 1; + instruction.mem_size = 63; instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, opwidth, length)?; } } else if r == 2 { @@ -8975,6 +9237,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else { instruction.opcode = Opcode::LGDT; instruction.operand_count = 1; + instruction.mem_size = 63; instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, opwidth, length)?; } } else if r == 3 { @@ -9039,6 +9302,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else { instruction.opcode = Opcode::LIDT; instruction.operand_count = 1; + instruction.mem_size = 63; instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, opwidth, length)?; } } else if r == 4 { @@ -9046,6 +9310,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter // spec suggets this might do something different for f.ex rdi? instruction.opcode = Opcode::SMSW; instruction.operand_count = 1; + instruction.mem_size = 2; instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 2, length)?; } else if r == 5 { let mod_bits = modrm >> 6; @@ -9055,6 +9320,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } instruction.opcode = Opcode::RSTORSSP; instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 8, length)?; + instruction.mem_size = 8; instruction.operand_count = 1; return Ok(()); } @@ -9156,6 +9422,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else if r == 6 { instruction.opcode = Opcode::LMSW; instruction.operand_count = 1; + instruction.mem_size = 2; instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 2, length)?; } else if r == 7 { let mod_bits = modrm >> 6; @@ -9205,6 +9472,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } else { instruction.opcode = Opcode::INVLPG; instruction.operand_count = 1; + instruction.mem_size = 1; instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, opwidth, length)?; } } else { @@ -9232,6 +9500,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } }; instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 1 /* opwidth */, length)?; + instruction.mem_size = 64; instruction.operand_count = 1; } else { instruction.opcode = match (modrm >> 3) & 7 { @@ -9286,6 +9555,9 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter 4 }; instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, opwidth, length)?; + if instruction.operands[0] != OperandSpec::RegMMM { + instruction.mem_size = opwidth; + } instruction.operand_count = 1; return Ok(()); } @@ -9365,6 +9637,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter instruction.opcode = Opcode::CLRSSBSY; instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 8, length)?; instruction.operand_count = 1; + instruction.mem_size = 8; return Ok(()); } _ => { @@ -9426,17 +9699,20 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter return Err(DecodeError::InvalidOperand); } instruction.operand_count = 1; - instruction.opcode = [ - Opcode::FXSAVE, - Opcode::FXRSTOR, - Opcode::LDMXCSR, - Opcode::STMXCSR, - Opcode::XSAVE, - Opcode::XRSTOR, - Opcode::XSAVEOPT, - Opcode::CLFLUSH, + let (opcode, mem_size) = [ + (Opcode::FXSAVE, 63), + (Opcode::FXRSTOR, 63), + (Opcode::LDMXCSR, 4), + (Opcode::STMXCSR, 4), + (Opcode::XSAVE, 63), + (Opcode::XRSTOR, 63), + (Opcode::XSAVEOPT, 63), + (Opcode::CLFLUSH, 64), ][r as usize]; + instruction.opcode = opcode; + instruction.mem_size = mem_size; instruction.operands[0] = read_M(&mut bytes_iter, instruction, modrm, length)?; + instruction.mem_size = mem_size; } } OperandCode::ModRM_0x0fba => { @@ -9652,6 +9928,7 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter if let OperandSpec::RegMMM = instruction.operands[1] { return Err(DecodeError::InvalidOperand); } + instruction.mem_size = 64; if instruction.prefixes.address_size() { instruction.modrm_rrr.bank = RegisterBank::D; } else { @@ -9690,13 +9967,22 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i enum OperandCodeX87 { Est, St_Est, + St_Edst, + St_Eqst, St_Ew, + St_Mw, St_Md, - Md, + St_Mq, + St_Mm, Ew, Est_St, + Edst_St, + Eqst_St, Ed_St, + Mw_St, Md_St, + Mq_St, + Mm_St, Ex87S, Nothing, } @@ -9708,20 +9994,20 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i let (opcode, x87_operands) = match operand_code { OperandCode::x87_d8 => { match r { - 0 => (Opcode::FADD, OperandCodeX87::St_Est), - 1 => (Opcode::FMUL, OperandCodeX87::St_Est), - 2 => (Opcode::FCOM, OperandCodeX87::St_Est), - 3 => (Opcode::FCOMP, OperandCodeX87::St_Est), - 4 => (Opcode::FSUB, OperandCodeX87::St_Est), - 5 => (Opcode::FSUBR, OperandCodeX87::St_Est), - 6 => (Opcode::FDIV, OperandCodeX87::St_Est), - 7 => (Opcode::FDIVR, OperandCodeX87::St_Est), + 0 => (Opcode::FADD, OperandCodeX87::St_Edst), + 1 => (Opcode::FMUL, OperandCodeX87::St_Edst), + 2 => (Opcode::FCOM, OperandCodeX87::St_Edst), + 3 => (Opcode::FCOMP, OperandCodeX87::St_Edst), + 4 => (Opcode::FSUB, OperandCodeX87::St_Edst), + 5 => (Opcode::FSUBR, OperandCodeX87::St_Edst), + 6 => (Opcode::FDIV, OperandCodeX87::St_Edst), + 7 => (Opcode::FDIVR, OperandCodeX87::St_Edst), _ => { unreachable!("impossible r"); } } } OperandCode::x87_d9 => { match r { - 0 => (Opcode::FLD, OperandCodeX87::St_Est), + 0 => (Opcode::FLD, OperandCodeX87::St_Edst), 1 => { if modrm >= 0xc0 { (Opcode::FXCH, OperandCodeX87::St_Est) @@ -9744,7 +10030,7 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i if modrm >= 0xc0 { (Opcode::FSTPNCE, OperandCodeX87::Est_St) } else { - (Opcode::FSTP, OperandCodeX87::Est_St) + (Opcode::FSTP, OperandCodeX87::Edst_St) } }, 4 => { @@ -9878,8 +10164,8 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i 1 => (Opcode::FISTTP, OperandCodeX87::Md_St), 2 => (Opcode::FIST, OperandCodeX87::Md_St), 3 => (Opcode::FISTP, OperandCodeX87::Md_St), - 5 => (Opcode::FLD, OperandCodeX87::St_Md), // 80bit - 7 => (Opcode::FSTP, OperandCodeX87::Md_St), // 80bit + 5 => (Opcode::FLD, OperandCodeX87::St_Mm), // 80bit + 7 => (Opcode::FSTP, OperandCodeX87::Mm_St), // 80bit _ => { return Err(DecodeError::InvalidOpcode); } @@ -9891,26 +10177,26 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i // mod=11 swaps operand order for some instructions if modrm >= 0xc0 { match r { - 0 => (Opcode::FADD, OperandCodeX87::Est_St), - 1 => (Opcode::FMUL, OperandCodeX87::Est_St), - 2 => (Opcode::FCOM, OperandCodeX87::St_Est), - 3 => (Opcode::FCOMP, OperandCodeX87::St_Est), - 4 => (Opcode::FSUBR, OperandCodeX87::Est_St), - 5 => (Opcode::FSUB, OperandCodeX87::Est_St), - 6 => (Opcode::FDIVR, OperandCodeX87::Est_St), - 7 => (Opcode::FDIV, OperandCodeX87::Est_St), + 0 => (Opcode::FADD, OperandCodeX87::Eqst_St), + 1 => (Opcode::FMUL, OperandCodeX87::Eqst_St), + 2 => (Opcode::FCOM, OperandCodeX87::St_Eqst), + 3 => (Opcode::FCOMP, OperandCodeX87::St_Eqst), + 4 => (Opcode::FSUBR, OperandCodeX87::Eqst_St), + 5 => (Opcode::FSUB, OperandCodeX87::Eqst_St), + 6 => (Opcode::FDIVR, OperandCodeX87::Eqst_St), + 7 => (Opcode::FDIV, OperandCodeX87::Eqst_St), _ => { unreachable!("impossible r"); } } } else { match r { - 0 => (Opcode::FADD, OperandCodeX87::St_Est), - 1 => (Opcode::FMUL, OperandCodeX87::St_Est), - 2 => (Opcode::FCOM, OperandCodeX87::St_Est), - 3 => (Opcode::FCOMP, OperandCodeX87::St_Est), - 4 => (Opcode::FSUB, OperandCodeX87::St_Est), - 5 => (Opcode::FSUBR, OperandCodeX87::St_Est), - 6 => (Opcode::FDIV, OperandCodeX87::St_Est), - 7 => (Opcode::FDIVR, OperandCodeX87::St_Est), + 0 => (Opcode::FADD, OperandCodeX87::St_Eqst), + 1 => (Opcode::FMUL, OperandCodeX87::St_Eqst), + 2 => (Opcode::FCOM, OperandCodeX87::St_Eqst), + 3 => (Opcode::FCOMP, OperandCodeX87::St_Eqst), + 4 => (Opcode::FSUB, OperandCodeX87::St_Eqst), + 5 => (Opcode::FSUBR, OperandCodeX87::St_Eqst), + 6 => (Opcode::FDIV, OperandCodeX87::St_Eqst), + 7 => (Opcode::FDIVR, OperandCodeX87::St_Eqst), _ => { unreachable!("impossible r"); } } } @@ -9930,13 +10216,13 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i } } else { match r { - 0 => (Opcode::FLD, OperandCodeX87::St_Est), - 1 => (Opcode::FISTTP, OperandCodeX87::Est_St), - 2 => (Opcode::FST, OperandCodeX87::Est_St), - 3 => (Opcode::FSTP, OperandCodeX87::Est_St), - 4 => (Opcode::FRSTOR, OperandCodeX87::Md), // TODO: m94/108byte + 0 => (Opcode::FLD, OperandCodeX87::St_Eqst), + 1 => (Opcode::FISTTP, OperandCodeX87::Eqst_St), + 2 => (Opcode::FST, OperandCodeX87::Eqst_St), + 3 => (Opcode::FSTP, OperandCodeX87::Eqst_St), + 4 => (Opcode::FRSTOR, OperandCodeX87::Ex87S), 5 => (Opcode::Invalid, OperandCodeX87::Nothing), - 6 => (Opcode::FNSAVE, OperandCodeX87::Est), + 6 => (Opcode::FNSAVE, OperandCodeX87::Ex87S), 7 => (Opcode::FNSTSW, OperandCodeX87::Ew), _ => { unreachable!("impossible r"); } } @@ -10000,14 +10286,14 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i } } else { match r { - 0 => (Opcode::FILD, OperandCodeX87::St_Est), - 1 => (Opcode::FISTTP, OperandCodeX87::Est_St), - 2 => (Opcode::FIST, OperandCodeX87::Est_St), - 3 => (Opcode::FISTP, OperandCodeX87::Est_St), - 4 => (Opcode::FBLD, OperandCodeX87::St_Est), - 5 => (Opcode::FILD, OperandCodeX87::St_Est), - 6 => (Opcode::FBSTP, OperandCodeX87::Est_St), - 7 => (Opcode::FISTP, OperandCodeX87::Est_St), + 0 => (Opcode::FILD, OperandCodeX87::St_Mw), + 1 => (Opcode::FISTTP, OperandCodeX87::Mw_St), + 2 => (Opcode::FIST, OperandCodeX87::Mw_St), + 3 => (Opcode::FISTP, OperandCodeX87::Mw_St), + 4 => (Opcode::FBLD, OperandCodeX87::St_Mm), + 5 => (Opcode::FILD, OperandCodeX87::St_Mq), + 6 => (Opcode::FBSTP, OperandCodeX87::Mm_St), + 7 => (Opcode::FISTP, OperandCodeX87::Mq_St), _ => { unreachable!("impossible r"); } } } @@ -10020,7 +10306,7 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } - // TODO: support 80-bit operands + match x87_operands { OperandCodeX87::Est => { instruction.operands[0] = read_E_st(&mut bytes_iter, instruction, modrm, length)?; @@ -10032,10 +10318,51 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i instruction.operands[1] = read_E_st(&mut bytes_iter, instruction, modrm, length)?; instruction.operand_count = 2; } + OperandCodeX87::St_Edst => { + instruction.operands[0] = OperandSpec::RegRRR; + instruction.modrm_rrr = RegSpec::st(0); + instruction.operands[1] = read_E_st(&mut bytes_iter, instruction, modrm, length)?; + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 4; + } + instruction.operand_count = 2; + } + OperandCodeX87::St_Eqst => { + instruction.operands[0] = OperandSpec::RegRRR; + instruction.modrm_rrr = RegSpec::st(0); + instruction.operands[1] = read_E_st(&mut bytes_iter, instruction, modrm, length)?; + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 8; + } + instruction.operand_count = 2; + } OperandCodeX87::St_Ew => { instruction.operands[0] = OperandSpec::RegRRR; instruction.modrm_rrr = RegSpec::st(0); instruction.operands[1] = read_E(&mut bytes_iter, instruction, modrm, 2, length)?; + if instruction.operands[1] != OperandSpec::RegMMM { + instruction.mem_size = 2; + } + instruction.operand_count = 2; + } + OperandCodeX87::St_Mm => { + instruction.operands[0] = OperandSpec::RegRRR; + instruction.modrm_rrr = RegSpec::st(0); + instruction.operands[1] = read_E(&mut bytes_iter, instruction, modrm, 4, length)?; + if instruction.operands[1] == OperandSpec::RegMMM { + return Err(DecodeError::InvalidOperand); + } + instruction.mem_size = 10; + instruction.operand_count = 2; + } + OperandCodeX87::St_Mq => { + instruction.operands[0] = OperandSpec::RegRRR; + instruction.modrm_rrr = RegSpec::st(0); + instruction.operands[1] = read_E(&mut bytes_iter, instruction, modrm, 4, length)?; + if instruction.operands[1] == OperandSpec::RegMMM { + return Err(DecodeError::InvalidOperand); + } + instruction.mem_size = 8; instruction.operand_count = 2; } OperandCodeX87::St_Md => { @@ -10045,18 +10372,25 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } + instruction.mem_size = 4; instruction.operand_count = 2; } - OperandCodeX87::Md => { - instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 4, length)?; - if instruction.operands[0] == OperandSpec::RegMMM { + OperandCodeX87::St_Mw => { + instruction.operands[0] = OperandSpec::RegRRR; + instruction.modrm_rrr = RegSpec::st(0); + instruction.operands[1] = read_E(&mut bytes_iter, instruction, modrm, 4, length)?; + if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } - instruction.operand_count = 1; + instruction.mem_size = 2; + instruction.operand_count = 2; } OperandCodeX87::Ew => { instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 2, length)?; instruction.operand_count = 1; + if instruction.operands[0] != OperandSpec::RegMMM { + instruction.mem_size = 2; + } } OperandCodeX87::Est_St => { instruction.operands[0] = read_E_st(&mut bytes_iter, instruction, modrm, length)?; @@ -10064,10 +10398,51 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i instruction.modrm_rrr = RegSpec::st(0); instruction.operand_count = 2; } + OperandCodeX87::Edst_St => { + instruction.operands[0] = read_E_st(&mut bytes_iter, instruction, modrm, length)?; + instruction.operands[1] = OperandSpec::RegRRR; + instruction.modrm_rrr = RegSpec::st(0); + instruction.operand_count = 2; + if instruction.operands[0] != OperandSpec::RegMMM { + instruction.mem_size = 4; + } + } + OperandCodeX87::Eqst_St => { + instruction.operands[0] = read_E_st(&mut bytes_iter, instruction, modrm, length)?; + instruction.operands[1] = OperandSpec::RegRRR; + instruction.modrm_rrr = RegSpec::st(0); + instruction.operand_count = 2; + if instruction.operands[0] != OperandSpec::RegMMM { + instruction.mem_size = 8; + } + } OperandCodeX87::Ed_St => { instruction.operands[0] = read_E_st(&mut bytes_iter, instruction, modrm, length)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.modrm_rrr = RegSpec::st(0); + if instruction.operands[0] != OperandSpec::RegMMM { + instruction.mem_size = 4; + } + instruction.operand_count = 2; + } + OperandCodeX87::Mm_St => { + instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 4, length)?; + if instruction.operands[0] == OperandSpec::RegMMM { + return Err(DecodeError::InvalidOperand); + } + instruction.mem_size = 10; + instruction.operands[1] = OperandSpec::RegRRR; + instruction.modrm_rrr = RegSpec::st(0); + instruction.operand_count = 2; + } + OperandCodeX87::Mq_St => { + instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 4, length)?; + if instruction.operands[0] == OperandSpec::RegMMM { + return Err(DecodeError::InvalidOperand); + } + instruction.mem_size = 8; + instruction.operands[1] = OperandSpec::RegRRR; + instruction.modrm_rrr = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Md_St => { @@ -10075,6 +10450,17 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } + instruction.mem_size = 4; + instruction.operands[1] = OperandSpec::RegRRR; + instruction.modrm_rrr = RegSpec::st(0); + instruction.operand_count = 2; + } + OperandCodeX87::Mw_St => { + instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 4, length)?; + if instruction.operands[0] == OperandSpec::RegMMM { + return Err(DecodeError::InvalidOperand); + } + instruction.mem_size = 2; instruction.operands[1] = OperandSpec::RegRRR; instruction.modrm_rrr = RegSpec::st(0); instruction.operand_count = 2; @@ -10082,6 +10468,10 @@ fn decode_x87<T: Iterator<Item=u8>>(_decoder: &InstDecoder, mut bytes_iter: T, i OperandCodeX87::Ex87S => { instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 4, length)?; instruction.operand_count = 1; + if instruction.operands[0] == OperandSpec::RegMMM { + return Err(DecodeError::InvalidOperand); + } + instruction.mem_size = 63; } OperandCodeX87::Nothing => { instruction.operand_count = 0; diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs index 7a58fe6..6db99a1 100644 --- a/src/long_mode/vex.rs +++ b/src/long_mode/vex.rs @@ -61,6 +61,7 @@ enum VEXOperandCode { Ed_G_xmm_imm8, Eq_G_xmm_imm8, G_Ex_V_xmm, + G_Ey_V_xmm, G_Ey_V_ymm, G_E_xmm, G_E_xmm_imm8, @@ -373,6 +374,11 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOperand); } + if instruction.opcode == Opcode::VMOVSS { + instruction.mem_size = 4; + } else { + instruction.mem_size = 8; + } instruction.operands[1] = other; instruction.operand_count = 2; } @@ -397,6 +403,11 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOperand); } + if instruction.opcode == Opcode::VMOVSS { + instruction.mem_size = 4; + } else { + instruction.mem_size = 8; + } instruction.operands[0] = other; instruction.operands[1] = instruction.operands[2]; instruction.operand_count = 2; @@ -416,6 +427,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = read_E_xmm(bytes, instruction, modrm, length)?; + instruction.mem_size = 4; instruction.operand_count = 3; Ok(()) } @@ -431,6 +443,7 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = read_E_xmm(bytes, instruction, modrm, length)?; + instruction.mem_size = 8; instruction.operand_count = 3; Ok(()) } @@ -449,7 +462,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[2] = OperandSpec::ImmU8; - instruction.mem_size = 1; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 1; + } instruction.operand_count = 3; instruction.imm = read_imm_unsigned(bytes, 1, length)?; Ok(()) @@ -466,7 +481,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[2] = OperandSpec::ImmU8; - instruction.mem_size = 2; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 2; + } instruction.operand_count = 3; instruction.imm = read_imm_unsigned(bytes, 1, length)?; Ok(()) @@ -483,7 +500,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[2] = OperandSpec::ImmU8; - instruction.mem_size = 4; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 4; + } instruction.operand_count = 3; instruction.imm = read_imm_unsigned(bytes, 1, length)?; Ok(()) @@ -500,7 +519,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[2] = OperandSpec::ImmU8; - instruction.mem_size = 8; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 8; + } instruction.operand_count = 3; instruction.imm = read_imm_unsigned(bytes, 1, length)?; Ok(()) @@ -517,6 +538,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.mem_size = 1; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 1; + } instruction.operand_count = 4; Ok(()) } @@ -532,6 +556,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.mem_size = 4; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 4; + } instruction.operand_count = 4; Ok(()) } @@ -546,7 +573,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[3] = OperandSpec::ImmU8; - instruction.mem_size = 8; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 8; + } instruction.operand_count = 4; Ok(()) } @@ -561,6 +590,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E(bytes, instruction, modrm, 8, length)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 8; + } instruction.operand_count = 2; Ok(()) } @@ -575,6 +607,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E(bytes, instruction, modrm, 4, length)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 4; + } instruction.operand_count = 2; Ok(()) } @@ -589,6 +624,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E(bytes, instruction, modrm, 8, length)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 8; + } instruction.operand_count = 2; Ok(()) } @@ -603,6 +641,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E(bytes, instruction, modrm, 4, length)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 4; + } instruction.operand_count = 2; Ok(()) } @@ -637,7 +678,11 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst if let OperandSpec::RegMMM = mem_oper { instruction.modrm_mmm.bank = RegisterBank::X; } else { - instruction.mem_size = 8; + if instruction.opcode == Opcode::VCVTSS2SI { + instruction.mem_size = 4; + } else { + instruction.mem_size = 8; + } } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; @@ -666,6 +711,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst /* and this is always accepted */ } } + if mem_oper != OperandSpec::RegMMM { + if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD || instruction.opcode == Opcode::VMOVHPS { + instruction.mem_size = 8; + } else { + instruction.mem_size = 16; + } + } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; @@ -737,10 +789,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[2] = OperandSpec::ImmU8; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 16; + } instruction.operand_count = 3; Ok(()) } - _op @ VEXOperandCode::E_xmm_G_ymm_imm8 => { + VEXOperandCode::E_xmm_G_ymm_imm8 => { if instruction.vex_reg.num != 0 { instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOperand); @@ -753,6 +808,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[2] = OperandSpec::ImmU8; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 16; + } instruction.operand_count = 3; Ok(()) } @@ -818,10 +876,19 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + if [Opcode::VBROADCASTSS, Opcode::VUCOMISS, Opcode::VCOMISS].contains(&instruction.opcode) { + instruction.mem_size = 4; + } else if [Opcode::VMOVDDUP, Opcode::VUCOMISD, Opcode::VCOMISD, Opcode::VCVTPS2PD, Opcode::VMOVQ].contains(&instruction.opcode) { + instruction.mem_size = 8; + } else { + instruction.mem_size = 16; + }; + } instruction.operand_count = 2; Ok(()) } - _op @ VEXOperandCode::G_xmm_E_xmm => { + VEXOperandCode::G_xmm_E_xmm => { if instruction.vex_reg.num != 0 { instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOperand); @@ -832,10 +899,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 16; + } instruction.operand_count = 2; Ok(()) } - _op @ VEXOperandCode::G_xmm_E_ymm => { + VEXOperandCode::G_xmm_E_ymm => { if instruction.vex_reg.num != 0 { instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOperand); @@ -846,6 +916,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 32; + } instruction.operand_count = 2; Ok(()) } @@ -866,10 +939,19 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + if [Opcode::VBROADCASTSS].contains(&instruction.opcode) { + instruction.mem_size = 4; + } else if [Opcode::VBROADCASTSD].contains(&instruction.opcode) { + instruction.mem_size = 8; + } else { + instruction.mem_size = 16; + } + } instruction.operand_count = 2; Ok(()) } - _op @ VEXOperandCode::G_ymm_E_ymm => { + VEXOperandCode::G_ymm_E_ymm => { if instruction.vex_reg.num != 0 { instruction.opcode = Opcode::Invalid; return Err(DecodeError::InvalidOperand); @@ -880,6 +962,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 32; + } instruction.operand_count = 2; Ok(()) } @@ -905,6 +990,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 32; + } instruction.operand_count = 2; Ok(()) } @@ -930,6 +1018,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 32; + } instruction.operand_count = 2; Ok(()) } @@ -947,6 +1038,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 32; + } instruction.operands[2] = mem_oper; instruction.operand_count = 3; Ok(()) @@ -962,6 +1056,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[3] = OperandSpec::ImmU8; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 32; + } instruction.operand_count = 4; Ok(()) } @@ -977,6 +1074,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegRRR; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 32; + } instruction.operand_count = 3; Ok(()) } @@ -995,6 +1095,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD { + instruction.mem_size = 8; + } else { + instruction.mem_size = 16; + } + } instruction.operand_count = 3; Ok(()) } @@ -1006,6 +1113,15 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + if [Opcode::VSQRTSS, Opcode::VADDSS, Opcode::VMULSS, Opcode::VSUBSS, Opcode::VMINSS, Opcode::VDIVSS, Opcode::VMAXSS].contains(&instruction.opcode) { + instruction.mem_size = 4; + } else if [Opcode::VSQRTSD, Opcode::VADDSD, Opcode::VMULSD, Opcode::VSUBSD, Opcode::VMINSD, Opcode::VDIVSD, Opcode::VMAXSD].contains(&instruction.opcode) { + instruction.mem_size = 8; + } else { + instruction.mem_size = 16; + } + } instruction.operand_count = 3; Ok(()) } @@ -1017,6 +1133,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 4; + } instruction.operand_count = 3; Ok(()) } @@ -1028,6 +1147,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 8; + } instruction.operand_count = 3; Ok(()) } @@ -1041,6 +1163,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[3] = OperandSpec::ImmU8; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 16; + } instruction.operand_count = 4; Ok(()) } @@ -1055,6 +1180,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[3] = OperandSpec::ImmU8; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 16; + } instruction.operand_count = 4; Ok(()) } @@ -1070,6 +1198,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegRRR; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 16; + } instruction.operand_count = 3; Ok(()) } @@ -1083,6 +1214,25 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operands[2] = OperandSpec::RegVex; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 4; + } + instruction.operand_count = 3; + Ok(()) + } + VEXOperandCode::G_Ey_V_xmm => { + let modrm = read_modrm(bytes, length)?; + instruction.modrm_rrr = + RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X); + let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?; + instruction.vex_reg.bank = RegisterBank::X; + instruction.sib_index.bank = RegisterBank::Y; + instruction.operands[0] = OperandSpec::RegRRR; + instruction.operands[1] = mem_oper; + instruction.operands[2] = OperandSpec::RegVex; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 4; + } instruction.operand_count = 3; Ok(()) } @@ -1096,6 +1246,13 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operands[2] = OperandSpec::RegVex; + if mem_oper != OperandSpec::RegMMM { + if instruction.opcode == Opcode::VPGATHERDD { + instruction.mem_size = 4; + } else { + instruction.mem_size = 8; + } + } instruction.operand_count = 3; Ok(()) } @@ -1113,6 +1270,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = opwidth; + } instruction.operand_count = 3; Ok(()) } @@ -1130,6 +1290,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operands[2] = OperandSpec::RegVex; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = opwidth; + } instruction.operand_count = 3; Ok(()) } @@ -1147,6 +1310,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[2] = OperandSpec::ImmI8; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = opwidth; + } instruction.operand_count = 3; Ok(()) } @@ -1178,6 +1344,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = mem_oper; instruction.operand_count = 2; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = opwidth; + } instruction.vex_reg.bank = bank; Ok(()) } @@ -1199,6 +1368,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst if let OperandSpec::RegMMM = mem_oper { return Err(DecodeError::InvalidOperand); } + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 4; + } instruction.operands[0] = mem_oper; instruction.operand_count = 1; Ok(()) @@ -1215,6 +1387,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[2] = OperandSpec::ImmU8; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 16; + } instruction.operand_count = 3; Ok(()) } @@ -1230,6 +1405,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[2] = OperandSpec::ImmU8; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 32; + } instruction.operand_count = 3; Ok(()) } @@ -1244,6 +1422,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(bytes, 1, length)? >> 4; instruction.operands[3] = OperandSpec::Reg4; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 32; + } instruction.operand_count = 4; Ok(()) } @@ -1258,6 +1439,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(bytes, 1, length)? >> 4; instruction.operands[3] = OperandSpec::Reg4; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 16; + } instruction.operand_count = 4; Ok(()) } @@ -1270,6 +1454,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 16; + } instruction.operand_count = 3; Ok(()) } @@ -1285,6 +1472,9 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(bytes, 1, length)?; instruction.operands[3] = OperandSpec::ImmI8; + if mem_oper != OperandSpec::RegMMM { + instruction.mem_size = 2; + } instruction.operand_count = 4; Ok(()) @@ -2556,7 +2746,7 @@ fn read_vex_instruction<T: Iterator<Item=u8>>(opcode_map: VEXOpcodeMap, bytes: & }) } else { (Opcode::VPGATHERQD, if L { - VEXOperandCode::G_Ey_V_ymm + VEXOperandCode::G_Ey_V_xmm } else { VEXOperandCode::G_Ex_V_xmm }) diff --git a/test/long_mode/mod.rs b/test/long_mode/mod.rs index 2dbd818..a3ad3a3 100644 --- a/test/long_mode/mod.rs +++ b/test/long_mode/mod.rs @@ -54,74 +54,74 @@ fn test_display_under(decoder: &InstDecoder, data: &[u8], expected: &'static str #[test] fn test_modrm_decode() { // just modrm - test_display(&[0x33, 0x08], "xor ecx, [rax]"); - test_display(&[0x33, 0x20], "xor esp, [rax]"); - test_display(&[0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor eax, [rip + 0x12345678]"); - test_display(&[0x33, 0x41, 0x23], "xor eax, [rcx + 0x23]"); - test_display(&[0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor eax, [rcx + 0x43650123]"); + test_display(&[0x33, 0x08], "xor ecx, dword [rax]"); + test_display(&[0x33, 0x20], "xor esp, dword [rax]"); + test_display(&[0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor eax, dword [rip + 0x12345678]"); + test_display(&[0x33, 0x41, 0x23], "xor eax, dword [rcx + 0x23]"); + test_display(&[0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor eax, dword [rcx + 0x43650123]"); test_display(&[0x33, 0xc1], "xor eax, ecx"); // modrm + rex.w - test_display(&[0x48, 0x33, 0x08], "xor rcx, [rax]"); - test_display(&[0x48, 0x33, 0x20], "xor rsp, [rax]"); - test_display(&[0x48, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor rax, [rip + 0x12345678]"); - test_display(&[0x48, 0x33, 0x41, 0x23], "xor rax, [rcx + 0x23]"); - test_display(&[0x48, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor rax, [rcx + 0x43650123]"); + test_display(&[0x48, 0x33, 0x08], "xor rcx, qword [rax]"); + test_display(&[0x48, 0x33, 0x20], "xor rsp, qword [rax]"); + test_display(&[0x48, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor rax, qword [rip + 0x12345678]"); + test_display(&[0x48, 0x33, 0x41, 0x23], "xor rax, qword [rcx + 0x23]"); + test_display(&[0x48, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor rax, qword [rcx + 0x43650123]"); test_display(&[0x48, 0x33, 0xc1], "xor rax, rcx"); // modrm + rex.r - test_display(&[0x44, 0x33, 0x08], "xor r9d, [rax]"); - test_display(&[0x44, 0x33, 0x20], "xor r12d, [rax]"); - test_display(&[0x44, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor r8d, [rip + 0x12345678]"); - test_display(&[0x44, 0x33, 0x41, 0x23], "xor r8d, [rcx + 0x23]"); - test_display(&[0x44, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor r8d, [rcx + 0x43650123]"); + test_display(&[0x44, 0x33, 0x08], "xor r9d, dword [rax]"); + test_display(&[0x44, 0x33, 0x20], "xor r12d, dword [rax]"); + test_display(&[0x44, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor r8d, dword [rip + 0x12345678]"); + test_display(&[0x44, 0x33, 0x41, 0x23], "xor r8d, dword [rcx + 0x23]"); + test_display(&[0x44, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor r8d, dword [rcx + 0x43650123]"); test_display(&[0x44, 0x33, 0xc1], "xor r8d, ecx"); // modrm + rex.rb - test_display(&[0x45, 0x33, 0x08], "xor r9d, [r8]"); - test_display(&[0x45, 0x33, 0x20], "xor r12d, [r8]"); - test_display(&[0x45, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor r8d, [rip + 0x12345678]"); - test_display(&[0x45, 0x33, 0x41, 0x23], "xor r8d, [r9 + 0x23]"); - test_display(&[0x45, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor r8d, [r9 + 0x43650123]"); + test_display(&[0x45, 0x33, 0x08], "xor r9d, dword [r8]"); + test_display(&[0x45, 0x33, 0x20], "xor r12d, dword [r8]"); + test_display(&[0x45, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor r8d, dword [rip + 0x12345678]"); + test_display(&[0x45, 0x33, 0x41, 0x23], "xor r8d, dword [r9 + 0x23]"); + test_display(&[0x45, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor r8d, dword [r9 + 0x43650123]"); test_display(&[0x45, 0x33, 0xc1], "xor r8d, r9d"); // sib - test_display(&[0x33, 0x04, 0x0a], "xor eax, [rdx + rcx * 1]"); - test_display(&[0x33, 0x04, 0x4a], "xor eax, [rdx + rcx * 2]"); - test_display(&[0x33, 0x04, 0x8a], "xor eax, [rdx + rcx * 4]"); - test_display(&[0x33, 0x04, 0xca], "xor eax, [rdx + rcx * 8]"); - test_display(&[0x33, 0x04, 0x20], "xor eax, [rax]"); - test_display(&[0x33, 0x04, 0x60], "xor eax, [rax]"); - test_display(&[0x33, 0x04, 0xa0], "xor eax, [rax]"); - test_display(&[0x33, 0x04, 0xe0], "xor eax, [rax]"); - test_display(&[0x42, 0x33, 0x04, 0x20], "xor eax, [rax + r12 * 1]"); - test_display(&[0x42, 0x33, 0x04, 0x60], "xor eax, [rax + r12 * 2]"); - test_display(&[0x42, 0x33, 0x04, 0xa0], "xor eax, [rax + r12 * 4]"); - test_display(&[0x42, 0x33, 0x04, 0xe0], "xor eax, [rax + r12 * 8]"); - test_display(&[0x43, 0x33, 0x04, 0x20], "xor eax, [r8 + r12 * 1]"); - test_display(&[0x43, 0x33, 0x04, 0x60], "xor eax, [r8 + r12 * 2]"); - test_display(&[0x43, 0x33, 0x04, 0xa0], "xor eax, [r8 + r12 * 4]"); - test_display(&[0x43, 0x33, 0x04, 0xe0], "xor eax, [r8 + r12 * 8]"); - test_display(&[0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "xor eax, [0x44332211]"); - test_display(&[0x41, 0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "xor eax, [0x44332211]"); - - test_display(&[0x33, 0x44, 0x65, 0x11], "xor eax, [rbp + 0x11]"); - test_display(&[0x41, 0x33, 0x44, 0x65, 0x11], "xor eax, [r13 + 0x11]"); - test_display(&[0x33, 0x84, 0xa5, 0x11, 0x22, 0x33, 0x44], "xor eax, [rbp + 0x44332211]"); - test_display(&[0x41, 0x33, 0x84, 0xa5, 0x11, 0x22, 0x33, 0x44], "xor eax, [r13 + 0x44332211]"); - test_display(&[0x33, 0x04, 0xe5, 0x11, 0x22, 0x33, 0x44], "xor eax, [0x44332211]"); - test_display(&[0x41, 0x33, 0x04, 0xe5, 0x11, 0x22, 0x33, 0x44], "xor eax, [0x44332211]"); + test_display(&[0x33, 0x04, 0x0a], "xor eax, dword [rdx + rcx * 1]"); + test_display(&[0x33, 0x04, 0x4a], "xor eax, dword [rdx + rcx * 2]"); + test_display(&[0x33, 0x04, 0x8a], "xor eax, dword [rdx + rcx * 4]"); + test_display(&[0x33, 0x04, 0xca], "xor eax, dword [rdx + rcx * 8]"); + test_display(&[0x33, 0x04, 0x20], "xor eax, dword [rax]"); + test_display(&[0x33, 0x04, 0x60], "xor eax, dword [rax]"); + test_display(&[0x33, 0x04, 0xa0], "xor eax, dword [rax]"); + test_display(&[0x33, 0x04, 0xe0], "xor eax, dword [rax]"); + test_display(&[0x42, 0x33, 0x04, 0x20], "xor eax, dword [rax + r12 * 1]"); + test_display(&[0x42, 0x33, 0x04, 0x60], "xor eax, dword [rax + r12 * 2]"); + test_display(&[0x42, 0x33, 0x04, 0xa0], "xor eax, dword [rax + r12 * 4]"); + test_display(&[0x42, 0x33, 0x04, 0xe0], "xor eax, dword [rax + r12 * 8]"); + test_display(&[0x43, 0x33, 0x04, 0x20], "xor eax, dword [r8 + r12 * 1]"); + test_display(&[0x43, 0x33, 0x04, 0x60], "xor eax, dword [r8 + r12 * 2]"); + test_display(&[0x43, 0x33, 0x04, 0xa0], "xor eax, dword [r8 + r12 * 4]"); + test_display(&[0x43, 0x33, 0x04, 0xe0], "xor eax, dword [r8 + r12 * 8]"); + test_display(&[0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [0x44332211]"); + test_display(&[0x41, 0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [0x44332211]"); + + test_display(&[0x33, 0x44, 0x65, 0x11], "xor eax, dword [rbp + 0x11]"); + test_display(&[0x41, 0x33, 0x44, 0x65, 0x11], "xor eax, dword [r13 + 0x11]"); + test_display(&[0x33, 0x84, 0xa5, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [rbp + 0x44332211]"); + test_display(&[0x41, 0x33, 0x84, 0xa5, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [r13 + 0x44332211]"); + test_display(&[0x33, 0x04, 0xe5, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [0x44332211]"); + test_display(&[0x41, 0x33, 0x04, 0xe5, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [0x44332211]"); // specifically sib with base == 0b101 // mod bits 00 - test_display(&[0x42, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, [r12 * 1 + 0x50403020]"); - test_display(&[0x43, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, [r12 * 1 + 0x50403020]"); + test_display(&[0x42, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [r12 * 1 + 0x50403020]"); + test_display(&[0x43, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [r12 * 1 + 0x50403020]"); // mod bits 01 - test_display(&[0x42, 0x33, 0x74, 0x25, 0x20], "xor esi, [rbp + r12 * 1 + 0x20]"); - test_display(&[0x43, 0x33, 0x74, 0x25, 0x20], "xor esi, [r13 + r12 * 1 + 0x20]"); + test_display(&[0x42, 0x33, 0x74, 0x25, 0x20], "xor esi, dword [rbp + r12 * 1 + 0x20]"); + test_display(&[0x43, 0x33, 0x74, 0x25, 0x20], "xor esi, dword [r13 + r12 * 1 + 0x20]"); // mod bits 10 - test_display(&[0x42, 0x33, 0xb4, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, [rbp + r12 * 1 + 0x50403020]"); - test_display(&[0x43, 0x33, 0xb4, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, [r13 + r12 * 1 + 0x50403020]"); + test_display(&[0x42, 0x33, 0xb4, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [rbp + r12 * 1 + 0x50403020]"); + test_display(&[0x43, 0x33, 0xb4, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [r13 + r12 * 1 + 0x50403020]"); } #[test] @@ -130,31 +130,31 @@ fn test_mmx() { test_display(&[0x0f, 0xf7, 0xc1], "maskmovq mm0, mm1"); test_invalid(&[0x0f, 0xf7, 0x01]); - test_display(&[0x4f, 0x0f, 0xe7, 0x03], "movntq [r11], mm0"); - test_display(&[0x0f, 0xe7, 0x03], "movntq [rbx], mm0"); + test_display(&[0x4f, 0x0f, 0xe7, 0x03], "movntq qword [r11], mm0"); + test_display(&[0x0f, 0xe7, 0x03], "movntq qword [rbx], mm0"); test_invalid(&[0x0f, 0xe7, 0xc3]); - test_display(&[0x4f, 0x0f, 0xc3, 0x03], "movnti [r11], r8"); + test_display(&[0x4f, 0x0f, 0xc3, 0x03], "movnti qword [r11], r8"); test_invalid(&[0x66, 0x0f, 0xc3, 0x03]); - test_display(&[0x0f, 0xc3, 0x03], "movnti [rbx], eax"); + test_display(&[0x0f, 0xc3, 0x03], "movnti dword [rbx], eax"); test_invalid(&[0x0f, 0xc3, 0xc3]); test_display(&[0x4f, 0x0f, 0x7e, 0xcf], "movd r15, mm1"); test_display(&[0x41, 0x0f, 0x7e, 0xcf], "movd r15d, mm1"); test_display(&[0x4f, 0x0f, 0x7f, 0xcf], "movq mm7, mm1"); - test_display(&[0x4f, 0x0f, 0x7f, 0x0f], "movq [r15], mm1"); + test_display(&[0x4f, 0x0f, 0x7f, 0x0f], "movq qword [r15], mm1"); test_display(&[0x0f, 0xc4, 0xc0, 0x14], "pinsrw mm0, eax, 0x14"); test_display(&[0x4f, 0x0f, 0xc4, 0xc0, 0x14], "pinsrw mm0, r8d, 0x14"); - test_display(&[0x4f, 0x0f, 0xc4, 0x00, 0x14], "pinsrw mm0, [r8], 0x14"); + test_display(&[0x4f, 0x0f, 0xc4, 0x00, 0x14], "pinsrw mm0, word [r8], 0x14"); test_display(&[0x4f, 0x0f, 0xd1, 0xcf], "psrlw mm1, mm7"); - test_display(&[0x4f, 0x0f, 0xd1, 0x00], "psrlw mm0, [r8]"); + test_display(&[0x4f, 0x0f, 0xd1, 0x00], "psrlw mm0, qword [r8]"); test_invalid(&[0x4f, 0x0f, 0xd7, 0x00]); test_display(&[0x4f, 0x0f, 0xd7, 0xcf], "pmovmskb r9d, mm7"); test_display(&[0x0f, 0x3a, 0x0f, 0xc1, 0x23], "palignr mm0, mm1, 0x23"); test_display(&[0x0f, 0xf9, 0xc2], "psubw mm0, mm2"); test_display(&[0x0f, 0xfd, 0xd2], "paddw mm2, mm2"); test_display(&[0x0f, 0x6f, 0xe9], "movq mm5, mm1"); - test_display(&[0x0f, 0xe5, 0x3d, 0xaa, 0xbb, 0xcc, 0x77], "pmulhw mm7, [rip + 0x77ccbbaa]"); + test_display(&[0x0f, 0xe5, 0x3d, 0xaa, 0xbb, 0xcc, 0x77], "pmulhw mm7, qword [rip + 0x77ccbbaa]"); test_display(&[0x0f, 0x38, 0x00, 0xda], "pshufb mm3, mm2"); @@ -208,19 +208,19 @@ fn test_cvt() { test_display(&[0x48, 0x0f, 0x2c, 0xcf], "cvttps2pi mm1, xmm7"); test_display(&[0x4f, 0x0f, 0x2c, 0xcf], "cvttps2pi mm1, xmm15"); test_display(&[0x4f, 0x0f, 0x2a, 0xcf], "cvtpi2ps xmm9, mm7"); - test_display(&[0x4f, 0x0f, 0x2a, 0x00], "cvtpi2ps xmm8, [r8]"); + test_display(&[0x4f, 0x0f, 0x2a, 0x00], "cvtpi2ps xmm8, qword [r8]"); test_display(&[0x4f, 0x66, 0x0f, 0x2a, 0xcf], "cvtpi2pd xmm1, mm7"); test_display(&[0x66, 0x4f, 0x0f, 0x2a, 0xcf], "cvtpi2pd xmm9, mm7"); test_display(&[0x4f, 0xf3, 0x0f, 0x2a, 0xcf], "cvtsi2ss xmm1, edi"); test_display(&[0xf3, 0x4f, 0x0f, 0x2a, 0xcf], "cvtsi2ss xmm9, r15"); test_display(&[0x4f, 0xf2, 0x0f, 0x2a, 0xcf], "cvtsi2sd xmm1, edi"); test_display(&[0xf2, 0x4f, 0x0f, 0x2a, 0xcf], "cvtsi2sd xmm9, r15"); - test_display(&[0x4f, 0xf2, 0x0f, 0x2a, 0x00], "cvtsi2sd xmm0, [rax]"); - test_display(&[0xf2, 0x4f, 0x0f, 0x2a, 0x00], "cvtsi2sd xmm8, [r8]"); - test_display(&[0x4f, 0xf3, 0x0f, 0x2a, 0x00], "cvtsi2ss xmm0, [rax]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x2a, 0x00], "cvtsi2ss xmm8, [r8]"); - test_display(&[0x4f, 0x66, 0x0f, 0x2a, 0x00], "cvtpi2pd xmm0, [rax]"); - test_display(&[0x66, 0x4f, 0x0f, 0x2a, 0x00], "cvtpi2pd xmm8, [r8]"); + test_display(&[0x4f, 0xf2, 0x0f, 0x2a, 0x00], "cvtsi2sd xmm0, dword [rax]"); + test_display(&[0xf2, 0x4f, 0x0f, 0x2a, 0x00], "cvtsi2sd xmm8, qword [r8]"); + test_display(&[0x4f, 0xf3, 0x0f, 0x2a, 0x00], "cvtsi2ss xmm0, dword [rax]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x2a, 0x00], "cvtsi2ss xmm8, qword [r8]"); + test_display(&[0x4f, 0x66, 0x0f, 0x2a, 0x00], "cvtpi2pd xmm0, dword [rax]"); + test_display(&[0x66, 0x4f, 0x0f, 0x2a, 0x00], "cvtpi2pd xmm8, qword [r8]"); } #[test] @@ -231,22 +231,22 @@ fn test_aesni() { test_invalid_under(&InstDecoder::minimal(), bytes); } - test_instr(&[0x66, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, [rdi]"); + test_instr(&[0x66, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x38, 0xdb, 0xcf], "aesimc xmm9, xmm15"); - test_instr(&[0x66, 0x0f, 0x38, 0xdc, 0x0f], "aesenc xmm1, [rdi]"); + test_instr(&[0x66, 0x0f, 0x38, 0xdc, 0x0f], "aesenc xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x38, 0xdc, 0xcf], "aesenc xmm9, xmm15"); - test_instr(&[0x66, 0x0f, 0x38, 0xdd, 0x0f], "aesenclast xmm1, [rdi]"); + test_instr(&[0x66, 0x0f, 0x38, 0xdd, 0x0f], "aesenclast xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x38, 0xdd, 0xcf], "aesenclast xmm9, xmm15"); - test_instr(&[0x66, 0x0f, 0x38, 0xde, 0x0f], "aesdec xmm1, [rdi]"); + test_instr(&[0x66, 0x0f, 0x38, 0xde, 0x0f], "aesdec xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x38, 0xde, 0xcf], "aesdec xmm9, xmm15"); - test_instr(&[0x66, 0x0f, 0x38, 0xdf, 0x0f], "aesdeclast xmm1, [rdi]"); + test_instr(&[0x66, 0x0f, 0x38, 0xdf, 0x0f], "aesdeclast xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x38, 0xdf, 0xcf], "aesdeclast xmm9, xmm15"); - test_instr(&[0x66, 0x0f, 0x3a, 0xdf, 0x0f, 0xaa], "aeskeygenassist xmm1, [rdi], 0xaa"); + test_instr(&[0x66, 0x0f, 0x3a, 0xdf, 0x0f, 0xaa], "aeskeygenassist xmm1, xmmword [rdi], 0xaa"); test_instr(&[0x66, 0x4f, 0x0f, 0x3a, 0xdf, 0xcf, 0xaa], "aeskeygenassist xmm9, xmm15, 0xaa"); } @@ -258,40 +258,40 @@ fn test_sse2() { test_display_under(&InstDecoder::minimal(), bytes, text); } - test_instr(&[0xf2, 0x0f, 0x10, 0x0c, 0xc7], "movsd xmm1, [rdi + rax * 8]"); - test_instr(&[0xf2, 0x0f, 0x11, 0x0c, 0xc7], "movsd [rdi + rax * 8], xmm1"); - test_instr(&[0x66, 0x0f, 0x11, 0x0c, 0xc7], "movupd [rdi + rax * 8], xmm1"); - test_instr(&[0x66, 0x4f, 0x0f, 0x12, 0x03], "movlpd xmm8, [r11]"); // reg-mem is movlpd - test_instr(&[0x66, 0x4f, 0x0f, 0x13, 0x03], "movlpd [r11], xmm8"); + test_instr(&[0xf2, 0x0f, 0x10, 0x0c, 0xc7], "movsd xmm1, qword [rdi + rax * 8]"); + test_instr(&[0xf2, 0x0f, 0x11, 0x0c, 0xc7], "movsd qword [rdi + rax * 8], xmm1"); + test_instr(&[0x66, 0x0f, 0x11, 0x0c, 0xc7], "movupd xmmword [rdi + rax * 8], xmm1"); + test_instr(&[0x66, 0x4f, 0x0f, 0x12, 0x03], "movlpd xmm8, qword [r11]"); // reg-mem is movlpd + test_instr(&[0x66, 0x4f, 0x0f, 0x13, 0x03], "movlpd qword [r11], xmm8"); test_invalid(&[0x66, 0x4f, 0x0f, 0x13, 0xc3]); - test_instr(&[0x66, 0x4f, 0x0f, 0x14, 0x03], "unpcklpd xmm8, [r11]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x14, 0x03], "unpcklpd xmm8, xmmword [r11]"); test_instr(&[0x66, 0x4f, 0x0f, 0x14, 0xc3], "unpcklpd xmm8, xmm11"); - test_instr(&[0x66, 0x4f, 0x0f, 0x15, 0x03], "unpckhpd xmm8, [r11]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x15, 0x03], "unpckhpd xmm8, xmmword [r11]"); test_instr(&[0x66, 0x4f, 0x0f, 0x15, 0xc3], "unpckhpd xmm8, xmm11"); - test_instr(&[0x66, 0x4f, 0x0f, 0x16, 0x03], "movhpd xmm8, [r11]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x17, 0x03], "movhpd [r11], xmm8"); + test_instr(&[0x66, 0x4f, 0x0f, 0x16, 0x03], "movhpd xmm8, qword [r11]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x17, 0x03], "movhpd qword [r11], xmm8"); test_invalid(&[0x66, 0x4f, 0x0f, 0x17, 0xc3]); test_instr(&[0x66, 0x4f, 0x0f, 0x28, 0xd0], "movapd xmm10, xmm8"); - test_instr(&[0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, [r8]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, xmmword [r8]"); test_instr(&[0x66, 0x4f, 0x0f, 0x2a, 0xcf], "cvtpi2pd xmm9, mm7"); - test_instr(&[0x66, 0x4f, 0x0f, 0x2a, 0x0f], "cvtpi2pd xmm9, [r15]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x2a, 0x0f], "cvtpi2pd xmm9, qword [r15]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x2a, 0xcf], "cvtsi2sd xmm9, r15"); - test_instr(&[0xf2, 0x4f, 0x0f, 0x2a, 0x0f], "cvtsi2sd xmm9, [r15]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x2b, 0x0f], "movntpd [r15], xmm9"); + test_instr(&[0xf2, 0x4f, 0x0f, 0x2a, 0x0f], "cvtsi2sd xmm9, qword [r15]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x2b, 0x0f], "movntpd xmmword [r15], xmm9"); test_instr(&[0x66, 0x4f, 0x0f, 0x2c, 0xcf], "cvttpd2pi mm1, xmm15"); - test_instr(&[0x66, 0x4f, 0x0f, 0x2c, 0x0f], "cvttpd2pi mm1, [r15]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x2c, 0x0f], "cvttpd2pi mm1, xmmword [r15]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x2c, 0xcf], "cvttsd2si xmm9, xmm15"); - test_instr(&[0xf2, 0x4f, 0x0f, 0x2c, 0x0f], "cvttsd2si xmm9, [r15]"); + test_instr(&[0xf2, 0x4f, 0x0f, 0x2c, 0x0f], "cvttsd2si xmm9, qword [r15]"); test_instr(&[0x66, 0x4f, 0x0f, 0x2d, 0xcf], "cvtpd2pi mm1, xmm15"); - test_instr(&[0x66, 0x4f, 0x0f, 0x2d, 0x0f], "cvtpd2pi mm1, [r15]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x2d, 0x0f], "cvtpd2pi mm1, xmmword [r15]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x2d, 0xcf], "cvtsd2si xmm9, xmm15"); - test_instr(&[0xf2, 0x4f, 0x0f, 0x2d, 0x0f], "cvtsd2si xmm9, [r15]"); + test_instr(&[0xf2, 0x4f, 0x0f, 0x2d, 0x0f], "cvtsd2si xmm9, qword [r15]"); test_instr(&[0x66, 0x4f, 0x0f, 0x2e, 0xcf], "ucomisd xmm9, xmm15"); - test_instr(&[0x66, 0x4f, 0x0f, 0x2e, 0x0f], "ucomisd xmm9, [r15]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x2e, 0x0f], "ucomisd xmm9, qword [r15]"); test_instr(&[0x66, 0x4f, 0x0f, 0x2f, 0xcf], "comisd xmm9, xmm15"); - test_instr(&[0x66, 0x4f, 0x0f, 0x2f, 0x0f], "comisd xmm9, [r15]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x2f, 0x0f], "comisd xmm9, qword [r15]"); /* * .... 660f38 @@ -300,93 +300,92 @@ fn test_sse2() { test_invalid(&[0x66, 0x4f, 0x0f, 0x50, 0x01]); test_instr(&[0x66, 0x4f, 0x0f, 0x50, 0xc1], "movmskpd r8d, xmm9"); - test_instr(&[0x66, 0x4f, 0x0f, 0x51, 0x01], "sqrtpd xmm8, [r9]"); - test_instr(&[0xf2, 0x4f, 0x0f, 0x51, 0x01], "sqrtsd xmm8, [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x51, 0x01], "sqrtpd xmm8, xmmword [r9]"); + test_instr(&[0xf2, 0x4f, 0x0f, 0x51, 0x01], "sqrtsd xmm8, qword [r9]"); test_invalid(&[0x66, 0x4f, 0x0f, 0x52, 0x01]); test_invalid(&[0x66, 0x4f, 0x0f, 0x53, 0x01]); - test_instr(&[0x66, 0x4f, 0x0f, 0x54, 0x01], "andpd xmm8, [r9]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x55, 0x01], "andnpd xmm8, [r9]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x56, 0x01], "orpd xmm8, [r9]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x57, 0x01], "xorpd xmm8, [r9]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x58, 0x01], "addpd xmm8, [r9]"); - test_instr(&[0xf2, 0x4f, 0x0f, 0x58, 0x01], "addsd xmm8, [r9]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x59, 0x01], "mulpd xmm8, [r9]"); - test_instr(&[0xf2, 0x4f, 0x0f, 0x59, 0x01], "mulsd xmm8, [r9]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x5a, 0x01], "cvtpd2ps xmm8, [r9]"); - test_instr(&[0xf2, 0x4f, 0x0f, 0x5a, 0x01], "cvtsd2ss xmm8, [r9]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x5b, 0x01], "cvtps2dq xmm8, [r9]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x5c, 0x01], "subpd xmm8, [r9]"); - test_instr(&[0xf2, 0x4f, 0x0f, 0x5c, 0x01], "subsd xmm8, [r9]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x5d, 0x01], "minpd xmm8, [r9]"); - test_instr(&[0xf2, 0x4f, 0x0f, 0x5d, 0x01], "minsd xmm8, [r9]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x5e, 0x01], "divpd xmm8, [r9]"); - test_instr(&[0xf2, 0x4f, 0x0f, 0x5e, 0x01], "divsd xmm8, [r9]"); - test_instr(&[0x66, 0x4f, 0x0f, 0x5f, 0x01], "maxpd xmm8, [r9]"); - test_instr(&[0xf2, 0x4f, 0x0f, 0x5f, 0x01], "maxsd xmm8, [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x54, 0x01], "andpd xmm8, xmmword [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x55, 0x01], "andnpd xmm8, xmmword [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x56, 0x01], "orpd xmm8, xmmword [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x57, 0x01], "xorpd xmm8, xmmword [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x58, 0x01], "addpd xmm8, xmmword [r9]"); + test_instr(&[0xf2, 0x4f, 0x0f, 0x58, 0x01], "addsd xmm8, qword [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x59, 0x01], "mulpd xmm8, xmmword [r9]"); + test_instr(&[0xf2, 0x4f, 0x0f, 0x59, 0x01], "mulsd xmm8, qword [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x5a, 0x01], "cvtpd2ps xmm8, xmmword [r9]"); + test_instr(&[0xf2, 0x4f, 0x0f, 0x5a, 0x01], "cvtsd2ss xmm8, qword [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x5b, 0x01], "cvtps2dq xmm8, xmmword [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x5c, 0x01], "subpd xmm8, xmmword [r9]"); + test_instr(&[0xf2, 0x4f, 0x0f, 0x5c, 0x01], "subsd xmm8, qword [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x5d, 0x01], "minpd xmm8, xmmword [r9]"); + test_instr(&[0xf2, 0x4f, 0x0f, 0x5d, 0x01], "minsd xmm8, qword [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x5e, 0x01], "divpd xmm8, xmmword [r9]"); + test_instr(&[0xf2, 0x4f, 0x0f, 0x5e, 0x01], "divsd xmm8, qword [r9]"); + test_instr(&[0x66, 0x4f, 0x0f, 0x5f, 0x01], "maxpd xmm8, xmmword [r9]"); + test_instr(&[0xf2, 0x4f, 0x0f, 0x5f, 0x01], "maxsd xmm8, qword [r9]"); test_instr( &[0x66, 0x4f, 0x0f, 0x60, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "punpcklbw xmm11, [r12 + r11 * 4 - 0x334455cc]" + "punpcklbw xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x61, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "punpcklwd xmm11, [r12 + r11 * 4 - 0x334455cc]" + "punpcklwd xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x62, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "punpckldq xmm11, [r12 + r11 * 4 - 0x334455cc]" + "punpckldq xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x63, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "packsswb xmm11, [r12 + r11 * 4 - 0x334455cc]" + "packsswb xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x64, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "pcmpgtb xmm11, [r12 + r11 * 4 - 0x334455cc]" + "pcmpgtb xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x65, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "pcmpgtw xmm11, [r12 + r11 * 4 - 0x334455cc]" + "pcmpgtw xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x66, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "pcmpgtd xmm11, [r12 + r11 * 4 - 0x334455cc]" + "pcmpgtd xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x67, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "packuswb xmm11, [r12 + r11 * 4 - 0x334455cc]" + "packuswb xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x68, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "punpckhbw xmm11, [r12 + r11 * 4 - 0x334455cc]" + "punpckhbw xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x69, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "punpckhwd xmm11, [r12 + r11 * 4 - 0x334455cc]" + "punpckhwd xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x6a, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "punpckhdq xmm11, [r12 + r11 * 4 - 0x334455cc]" + "punpckhdq xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x6b, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "packssdw xmm11, [r12 + r11 * 4 - 0x334455cc]" + "packssdw xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x6c, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "punpcklqdq xmm11, [r12 + r11 * 4 - 0x334455cc]" + "punpcklqdq xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x6d, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "punpckhqdq xmm11, [r12 + r11 * 4 - 0x334455cc]" + "punpckhqdq xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); - // TODO: this needs to be clear that the operand is `dword` test_instr( &[0x66, 0x4f, 0x0f, 0x6e, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "movq xmm11, [r12 + r11 * 4 - 0x334455cc]" + "movq xmm11, qword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x6f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "movdqa xmm11, [r12 + r11 * 4 - 0x334455cc]" + "movdqa xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr(&[0x66, 0x48, 0x0f, 0x6e, 0xc0], "movq xmm0, rax"); @@ -415,25 +414,25 @@ fn test_sse2() { test_instr(&[0x66, 0x4f, 0x0f, 0x73, 0xf8, 0x8f], "pslldq xmm0, 0x8f"); test_instr(&[0x66, 0x0f, 0x7e, 0xc1], "movd ecx, xmm0"); test_instr(&[0x66, 0x48, 0x0f, 0x7e, 0xc1], "movq rcx, xmm0"); - test_instr(&[0x66, 0x48, 0x0f, 0x7e, 0x01], "movd [rcx], xmm0"); + test_instr(&[0x66, 0x48, 0x0f, 0x7e, 0x01], "movq qword [rcx], xmm0"); test_instr(&[0x66, 0x4f, 0x0f, 0x7e, 0xc1], "movq r9, xmm8"); test_instr( &[0x66, 0x4f, 0x0f, 0x7f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "movdqa [r12 + r11 * 4 - 0x334455cc], xmm11" + "movdqa xmmword [r12 + r11 * 4 - 0x334455cc], xmm11" ); test_instr(&[0x66, 0x0f, 0xc2, 0xc3, 0x08], "cmppd xmm0, xmm3, 0x8"); test_instr(&[0x66, 0x4f, 0x0f, 0xc2, 0xc3, 0x08], "cmppd xmm8, xmm11, 0x8"); - test_instr(&[0x66, 0x4f, 0x0f, 0xc2, 0x03, 0x08], "cmppd xmm8, [r11], 0x8"); + test_instr(&[0x66, 0x4f, 0x0f, 0xc2, 0x03, 0x08], "cmppd xmm8, xmmword [r11], 0x8"); test_instr(&[0xf2, 0x0f, 0xc2, 0xc3, 0x08], "cmpsd xmm0, xmm3, 0x8"); test_instr(&[0xf2, 0x4f, 0x0f, 0xc2, 0xc3, 0x08], "cmpsd xmm8, xmm11, 0x8"); - test_instr(&[0xf2, 0x4f, 0x0f, 0xc2, 0x03, 0x08], "cmpsd xmm8, [r11], 0x8"); + test_instr(&[0xf2, 0x4f, 0x0f, 0xc2, 0x03, 0x08], "cmpsd xmm8, qword [r11], 0x8"); test_instr(&[0x66, 0x0f, 0xc4, 0xc3, 0x08], "pinsrw xmm0, ebx, 0x8"); test_instr(&[0x66, 0x4f, 0x0f, 0xc4, 0xc3, 0x08], "pinsrw xmm8, r11d, 0x8"); - test_instr(&[0x66, 0x0f, 0xc4, 0x03, 0x08], "pinsrw xmm0, [rbx], 0x8"); - test_instr(&[0x66, 0x4f, 0x0f, 0xc4, 0x03, 0x08], "pinsrw xmm8, [r11], 0x8"); + test_instr(&[0x66, 0x0f, 0xc4, 0x03, 0x08], "pinsrw xmm0, word [rbx], 0x8"); + test_instr(&[0x66, 0x4f, 0x0f, 0xc4, 0x03, 0x08], "pinsrw xmm8, word [r11], 0x8"); // test_instr(&[0x66, 0x0f, 0xc5, 0xc3, 0x08], "pextrw eax, xmm3, 0x8"); // test_instr(&[0x66, 0x4f, 0x0f, 0xc5, 0xc3, 0x08], "pextrw r8d, xmm11, 0x8"); @@ -441,21 +440,21 @@ fn test_sse2() { // test_instr_invalid(&[0x66, 0x0f, 0xc5, 0x40, 0x08]); // test_instr_invalid(&[0x66, 0x0f, 0xc5, 0x80, 0x08]); - test_instr(&[0x66, 0x4f, 0x0f, 0xc6, 0x03, 0x08], "shufpd xmm8, [r11], 0x8"); - test_instr(&[0x66, 0x0f, 0xc6, 0x03, 0x08], "shufpd xmm0, [rbx], 0x8"); + test_instr(&[0x66, 0x4f, 0x0f, 0xc6, 0x03, 0x08], "shufpd xmm8, xmmword [r11], 0x8"); + test_instr(&[0x66, 0x0f, 0xc6, 0x03, 0x08], "shufpd xmm0, xmmword [rbx], 0x8"); test_instr(&[0x66, 0x0f, 0xc6, 0xc3, 0x08], "shufpd xmm0, xmm3, 0x8"); test_instr(&[0x66, 0x0f, 0xd1, 0xc1], "psrlw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xd1, 0x01], "psrlw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xd1, 0x01], "psrlw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd2, 0xc1], "psrld xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xd2, 0x01], "psrld xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xd2, 0x01], "psrld xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd3, 0xc1], "psrlq xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xd3, 0x01], "psrlq xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xd3, 0x01], "psrlq xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd4, 0xc1], "paddq xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xd4, 0x01], "paddq xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xd4, 0x01], "paddq xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd5, 0xc1], "pmullw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xd5, 0x01], "pmullw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xd5, 0x01], "pmullw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd6, 0xc1], "movq xmm1, xmm0"); - test_instr(&[0x66, 0x0f, 0xd6, 0x01], "movq [rcx], xmm0"); + test_instr(&[0x66, 0x0f, 0xd6, 0x01], "movq qword [rcx], xmm0"); test_invalid(&[0xf3, 0x4f, 0x0f, 0xd6, 0x03]); test_instr(&[0xf3, 0x4f, 0x0f, 0xd6, 0xc3], "movq2dq xmm8, mm3"); test_instr(&[0xf2, 0x4f, 0x0f, 0xd6, 0xc3], "movdq2q mm0, xmm11"); @@ -463,98 +462,98 @@ fn test_sse2() { test_instr(&[0x66, 0x4f, 0x0f, 0xd7, 0xc1], "pmovmskb r8d, xmm9"); test_invalid(&[0x66, 0x0f, 0xd7, 0x01]); test_instr(&[0x66, 0x0f, 0xd8, 0xc1], "psubusb xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xd8, 0x01], "psubusb xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xd8, 0x01], "psubusb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd9, 0xc1], "psubusw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xd9, 0x01], "psubusw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xd9, 0x01], "psubusw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xda, 0xc1], "pminub xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xda, 0x01], "pminub xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xda, 0x01], "pminub xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xdb, 0xc1], "pand xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xdb, 0x01], "pand xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xdb, 0x01], "pand xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xdc, 0xc1], "paddusb xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xdc, 0x01], "paddusb xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xdc, 0x01], "paddusb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xdd, 0xc1], "paddusw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xdd, 0x01], "paddusw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xdd, 0x01], "paddusw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xde, 0xc1], "pmaxub xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xde, 0x01], "pmaxub xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xde, 0x01], "pmaxub xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xdf, 0xc1], "pandn xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xdf, 0x01], "pandn xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xdf, 0x01], "pandn xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe0, 0xc1], "pavgb xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xe0, 0x01], "pavgb xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xe0, 0x01], "pavgb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe1, 0xc1], "psraw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xe1, 0x01], "psraw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xe1, 0x01], "psraw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe2, 0xc1], "psrad xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xe2, 0x01], "psrad xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xe2, 0x01], "psrad xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe3, 0xc1], "pavgw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xe3, 0x01], "pavgw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xe3, 0x01], "pavgw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe4, 0xc1], "pmulhuw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xe4, 0x01], "pmulhuw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xe4, 0x01], "pmulhuw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe5, 0xc1], "pmulhw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xe5, 0x01], "pmulhw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xe5, 0x01], "pmulhw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe6, 0xc1], "cvttpd2dq xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xe6, 0x01], "cvttpd2dq xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xe6, 0x01], "cvttpd2dq xmm0, xmmword [rcx]"); test_invalid(&[0x66, 0x0f, 0xe7, 0xc1]); - test_instr(&[0x66, 0x0f, 0xe7, 0x01], "movntdq [rcx], xmm0"); + test_instr(&[0x66, 0x0f, 0xe7, 0x01], "movntdq xmmword [rcx], xmm0"); test_instr(&[0x66, 0x0f, 0xe8, 0xc1], "psubsb xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xe8, 0x01], "psubsb xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xe8, 0x01], "psubsb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe9, 0xc1], "psubsw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xe9, 0x01], "psubsw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xe9, 0x01], "psubsw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xea, 0xc1], "pminsw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xea, 0x01], "pminsw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xea, 0x01], "pminsw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xeb, 0xc3], "por xmm0, xmm3"); test_instr(&[0x66, 0x0f, 0xeb, 0xc4], "por xmm0, xmm4"); test_instr(&[0x66, 0x0f, 0xeb, 0xd3], "por xmm2, xmm3"); - test_instr(&[0x66, 0x0f, 0xeb, 0x12], "por xmm2, [rdx]"); + test_instr(&[0x66, 0x0f, 0xeb, 0x12], "por xmm2, xmmword [rdx]"); test_instr(&[0x66, 0x0f, 0xeb, 0xc1], "por xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xeb, 0x01], "por xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xeb, 0x01], "por xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xec, 0xc1], "paddsb xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xec, 0x01], "paddsb xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xec, 0x01], "paddsb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xed, 0xc1], "paddsw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xed, 0x01], "paddsw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xed, 0x01], "paddsw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xee, 0xc1], "pmaxsw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xee, 0x01], "pmaxsw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xee, 0x01], "pmaxsw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xef, 0xc1], "pxor xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xef, 0x01], "pxor xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xef, 0x01], "pxor xmm0, xmmword [rcx]"); test_invalid(&[0x66, 0x0f, 0xf0, 0xc1]); test_invalid(&[0x66, 0x0f, 0xf0, 0x01]); test_instr(&[0x66, 0x0f, 0xf1, 0xc1], "psllw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xf1, 0x01], "psllw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xf1, 0x01], "psllw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf2, 0xc1], "pslld xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xf2, 0x01], "pslld xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xf2, 0x01], "pslld xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf3, 0xc1], "psllq xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xf3, 0x01], "psllq xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xf3, 0x01], "psllq xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf4, 0xc1], "pmuludq xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xf4, 0x01], "pmuludq xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xf4, 0x01], "pmuludq xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf5, 0xc1], "pmaddwd xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xf5, 0x01], "pmaddwd xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xf5, 0x01], "pmaddwd xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf6, 0xc1], "psadbw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xf6, 0x01], "psadbw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xf6, 0x01], "psadbw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf7, 0xc1], "maskmovdqu xmm0, xmm1"); test_invalid(&[0x66, 0x0f, 0xf7, 0x01]); test_instr(&[0x66, 0x0f, 0xf8, 0xc1], "psubb xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xf8, 0x01], "psubb xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xf8, 0x01], "psubb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf9, 0xc1], "psubw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xf9, 0x01], "psubw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xf9, 0x01], "psubw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xfa, 0xc1], "psubd xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xfa, 0x01], "psubd xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xfa, 0x01], "psubd xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xfb, 0xc1], "psubq xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xfb, 0x01], "psubq xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xfb, 0x01], "psubq xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xfc, 0xc1], "paddb xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xfc, 0x01], "paddb xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xfc, 0x01], "paddb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xfd, 0xc1], "paddw xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xfd, 0x01], "paddw xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xfd, 0x01], "paddw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xfe, 0xc1], "paddd xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0xfe, 0x01], "paddd xmm0, [rcx]"); + test_instr(&[0x66, 0x0f, 0xfe, 0x01], "paddd xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); test_instr(&[0xf2, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); test_instr(&[0xf3, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); - test_instr(&[0x66, 0x0f, 0xff, 0x01], "ud0 eax, [rcx]"); + test_instr(&[0x66, 0x0f, 0xff, 0x01], "ud0 eax, dword [rcx]"); test_instr(&[0x66, 0x4f, 0x0f, 0xff, 0xc1], "ud0 r8d, r9d"); test_instr(&[0x66, 0x0f, 0x74, 0xc1], "pcmpeqb xmm0, xmm1"); - test_instr(&[0x66, 0x0f, 0x74, 0x12], "pcmpeqb xmm2, [rdx]"); + test_instr(&[0x66, 0x0f, 0x74, 0x12], "pcmpeqb xmm2, xmmword [rdx]"); test_instr(&[0x66, 0x0f, 0xf8, 0xc8], "psubb xmm1, xmm0"); test_instr(&[0x66, 0x0f, 0xf8, 0xd0], "psubb xmm2, xmm0"); - test_instr(&[0x66, 0x0f, 0xf8, 0x12], "psubb xmm2, [rdx]"); + test_instr(&[0x66, 0x0f, 0xf8, 0x12], "psubb xmm2, xmmword [rdx]"); } #[test] @@ -573,38 +572,38 @@ fn test_sse3() { test_invalid_under(&InstDecoder::minimal().with_sse3(), bytes); test_invalid_under(&InstDecoder::default(), bytes); } - test_instr(&[0xf2, 0x0f, 0xf0, 0x0f], "lddqu xmm1, [rdi]"); + test_instr(&[0xf2, 0x0f, 0xf0, 0x0f], "lddqu xmm1, xmmword [rdi]"); test_instr_invalid(&[0xf2, 0x0f, 0xf0, 0xcf]); - test_instr(&[0xf2, 0x0f, 0xd0, 0x0f], "addsubps xmm1, [rdi]"); + test_instr(&[0xf2, 0x0f, 0xd0, 0x0f], "addsubps xmm1, xmmword [rdi]"); test_instr(&[0xf2, 0x0f, 0xd0, 0xcf], "addsubps xmm1, xmm7"); test_invalid(&[0xf3, 0x0f, 0xd0, 0x0f]); test_instr(&[0xf2, 0x4f, 0x0f, 0xd0, 0xcf], "addsubps xmm9, xmm15"); - test_instr(&[0x66, 0x0f, 0xd0, 0x0f], "addsubpd xmm1, [rdi]"); + test_instr(&[0x66, 0x0f, 0xd0, 0x0f], "addsubpd xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x0f, 0xd0, 0xcf], "addsubpd xmm1, xmm7"); test_instr(&[0x66, 0x4f, 0x0f, 0xd0, 0xcf], "addsubpd xmm9, xmm15"); - test_instr(&[0xf2, 0x0f, 0x7c, 0x0f], "haddps xmm1, [rdi]"); + test_instr(&[0xf2, 0x0f, 0x7c, 0x0f], "haddps xmm1, xmmword [rdi]"); test_instr(&[0xf2, 0x0f, 0x7c, 0xcf], "haddps xmm1, xmm7"); test_instr(&[0xf2, 0x4f, 0x0f, 0x7c, 0xcf], "haddps xmm9, xmm15"); - test_instr(&[0x66, 0x0f, 0x7c, 0x0f], "haddpd xmm1, [rdi]"); + test_instr(&[0x66, 0x0f, 0x7c, 0x0f], "haddpd xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x0f, 0x7c, 0xcf], "haddpd xmm1, xmm7"); test_instr(&[0x66, 0x4f, 0x0f, 0x7c, 0xcf], "haddpd xmm9, xmm15"); - test_instr(&[0xf2, 0x0f, 0x7d, 0x0f], "hsubps xmm1, [rdi]"); + test_instr(&[0xf2, 0x0f, 0x7d, 0x0f], "hsubps xmm1, xmmword [rdi]"); test_instr(&[0xf2, 0x0f, 0x7d, 0xcf], "hsubps xmm1, xmm7"); test_instr(&[0xf2, 0x4f, 0x0f, 0x7d, 0xcf], "hsubps xmm9, xmm15"); - test_instr(&[0x66, 0x0f, 0x7d, 0x0f], "hsubpd xmm1, [rdi]"); + test_instr(&[0x66, 0x0f, 0x7d, 0x0f], "hsubpd xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x0f, 0x7d, 0xcf], "hsubpd xmm1, xmm7"); test_instr(&[0x66, 0x4f, 0x0f, 0x7d, 0xcf], "hsubpd xmm9, xmm15"); - test_instr(&[0xf3, 0x0f, 0x12, 0x0f], "movsldup xmm1, [rdi]"); + test_instr(&[0xf3, 0x0f, 0x12, 0x0f], "movsldup xmm1, xmmword [rdi]"); test_instr(&[0xf3, 0x0f, 0x12, 0xcf], "movsldup xmm1, xmm7"); test_instr(&[0xf3, 0x4f, 0x0f, 0x12, 0xcf], "movsldup xmm9, xmm15"); - test_instr(&[0xf3, 0x0f, 0x16, 0x0f], "movshdup xmm1, [rdi]"); + test_instr(&[0xf3, 0x0f, 0x16, 0x0f], "movshdup xmm1, xmmword [rdi]"); test_instr(&[0xf3, 0x0f, 0x16, 0xcf], "movshdup xmm1, xmm7"); test_instr(&[0xf3, 0x4f, 0x0f, 0x16, 0xcf], "movshdup xmm9, xmm15"); - test_instr(&[0xf2, 0x0f, 0x12, 0x0f], "movddup xmm1, [rdi]"); + test_instr(&[0xf2, 0x0f, 0x12, 0x0f], "movddup xmm1, qword [rdi]"); test_instr(&[0xf2, 0x0f, 0x12, 0xcf], "movddup xmm1, xmm7"); test_instr(&[0xf2, 0x4f, 0x0f, 0x12, 0xcf], "movddup xmm9, xmm15"); @@ -634,24 +633,24 @@ fn test_sse4_2() { test_invalid_under(&InstDecoder::default(), bytes); } - test_instr(&[0x66, 0x0f, 0x38, 0x37, 0x03], "pcmpgtq xmm0, [rbx]"); + test_instr(&[0x66, 0x0f, 0x38, 0x37, 0x03], "pcmpgtq xmm0, xmmword [rbx]"); test_instr(&[0x66, 0x0f, 0x38, 0x37, 0xc3], "pcmpgtq xmm0, xmm3"); - test_instr(&[0xf2, 0x0f, 0x38, 0xf0, 0x06], "crc32 eax, [rsi]"); + test_instr(&[0xf2, 0x0f, 0x38, 0xf0, 0x06], "crc32 eax, byte [rsi]"); test_instr(&[0xf2, 0x0f, 0x38, 0xf0, 0xc6], "crc32 eax, dh"); - test_instr(&[0xf2, 0x0f, 0x38, 0xf1, 0x06], "crc32 eax, [rsi]"); + test_instr(&[0xf2, 0x0f, 0x38, 0xf1, 0x06], "crc32 eax, dword [rsi]"); test_instr(&[0xf2, 0x0f, 0x38, 0xf1, 0xc6], "crc32 eax, esi"); test_instr(&[0x66, 0xf2, 0x0f, 0x38, 0xf1, 0xc6], "crc32 eax, si"); test_instr(&[0x66, 0xf2, 0x48, 0x0f, 0x38, 0xf1, 0xc6], "crc32 rax, rsi"); test_instr(&[0x66, 0x0f, 0x3a, 0x60, 0xc6, 0x54], "pcmpestrm xmm0, xmm6, 0x54"); - test_instr(&[0x66, 0x0f, 0x3a, 0x60, 0x06, 0x54], "pcmpestrm xmm0, [rsi], 0x54"); + test_instr(&[0x66, 0x0f, 0x3a, 0x60, 0x06, 0x54], "pcmpestrm xmm0, xmmword [rsi], 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x61, 0xc6, 0x54], "pcmpestri xmm0, xmm6, 0x54"); - test_instr(&[0x66, 0x0f, 0x3a, 0x61, 0x06, 0x54], "pcmpestri xmm0, [rsi], 0x54"); + test_instr(&[0x66, 0x0f, 0x3a, 0x61, 0x06, 0x54], "pcmpestri xmm0, xmmword [rsi], 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x62, 0xc6, 0x54], "pcmpistrm xmm0, xmm6, 0x54"); - test_instr(&[0x66, 0x0f, 0x3a, 0x62, 0x06, 0x54], "pcmpistrm xmm0, [rsi], 0x54"); + test_instr(&[0x66, 0x0f, 0x3a, 0x62, 0x06, 0x54], "pcmpistrm xmm0, xmmword [rsi], 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x63, 0xc6, 0x54], "pcmpistri xmm0, xmm6, 0x54"); - test_instr(&[0x66, 0x0f, 0x3a, 0x63, 0x06, 0x54], "pcmpistri xmm0, [rsi], 0x54"); + test_instr(&[0x66, 0x0f, 0x3a, 0x63, 0x06, 0x54], "pcmpistri xmm0, xmmword [rsi], 0x54"); } #[test] @@ -671,116 +670,116 @@ fn test_sse4_1() { test_invalid_under(&InstDecoder::default(), bytes); } - test_instr(&[0x66, 0x0f, 0x3a, 0x0c, 0x11, 0x22], "blendps xmm2, [rcx], 0x22"); + test_instr(&[0x66, 0x0f, 0x3a, 0x0c, 0x11, 0x22], "blendps xmm2, xmmword [rcx], 0x22"); test_instr(&[0x66, 0x0f, 0x3a, 0x0c, 0xc1, 0x22], "blendps xmm0, xmm1, 0x22"); - test_instr(&[0x66, 0x0f, 0x3a, 0x0d, 0x11, 0x22], "blendpd xmm2, [rcx], 0x22"); + test_instr(&[0x66, 0x0f, 0x3a, 0x0d, 0x11, 0x22], "blendpd xmm2, xmmword [rcx], 0x22"); test_instr(&[0x66, 0x0f, 0x3a, 0x0d, 0xc1, 0x22], "blendpd xmm0, xmm1, 0x22"); - test_instr(&[0x66, 0x0f, 0x38, 0x10, 0x06], "pblendvb xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x10, 0x06], "pblendvb xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x10, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x14, 0x06], "blendvps xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x14, 0x06], "blendvps xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x14, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x15, 0x06], "blendvpd xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x15, 0x06], "blendvpd xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x15, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x17, 0x06], "ptest xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x17, 0x06], "ptest xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x17, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x20, 0x06], "pmovsxbw xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x20, 0x06], "pmovsxbw xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x20, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x21, 0x06], "pmovsxbd xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x21, 0x06], "pmovsxbd xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x21, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x22, 0x06], "pmovsxbq xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x22, 0x06], "pmovsxbq xmm0, word [rsi]"); test_invalid(&[0x0f, 0x38, 0x22, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x23, 0x06], "pmovsxwd xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x23, 0x06], "pmovsxwd xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x23, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x24, 0x06], "pmovsxwq xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x24, 0x06], "pmovsxwq xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x24, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x25, 0x06], "pmovsxdq xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x25, 0x06], "pmovsxdq xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x25, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x28, 0x06], "pmuldq xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x28, 0x06], "pmuldq xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x28, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x29, 0x06], "pcmpeqq xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x29, 0x06], "pcmpeqq xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x29, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x2a, 0x06], "movntdqa xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x2a, 0x06], "movntdqa xmm0, xmmword [rsi]"); test_invalid(&[0x66, 0x0f, 0x38, 0x2a, 0xc6]); test_invalid(&[0x0f, 0x38, 0x2a, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x2b, 0x06], "packusdw xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x2b, 0x06], "packusdw xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x2b, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x30, 0x06], "pmovzxbw xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x30, 0x06], "pmovzxbw xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x30, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x31, 0x06], "pmovzxbd xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x31, 0x06], "pmovzxbd xmm0, dword [rsi]"); test_invalid(&[0x0f, 0x38, 0x31, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x32, 0x06], "pmovzxbq xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x32, 0x06], "pmovzxbq xmm0, word [rsi]"); test_invalid(&[0x0f, 0x38, 0x32, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x33, 0x06], "pmovzxwd xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x33, 0x06], "pmovzxwd xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x33, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x34, 0x06], "pmovzxwq xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x34, 0x06], "pmovzxwq xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x34, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x35, 0x06], "pmovzxdq xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x35, 0x06], "pmovzxdq xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x35, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x38, 0x06], "pminsb xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x38, 0x06], "pminsb xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x38, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x39, 0x06], "pminsd xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x39, 0x06], "pminsd xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x39, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x3a, 0x06], "pminuw xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x3a, 0x06], "pminuw xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3a, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x3b, 0x06], "pminud xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x3b, 0x06], "pminud xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3b, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x3c, 0x06], "pmaxsb xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x3c, 0x06], "pmaxsb xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3c, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x3d, 0x06], "pmaxsd xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x3d, 0x06], "pmaxsd xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3d, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x3e, 0x06], "pmaxuw xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x3e, 0x06], "pmaxuw xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3e, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x3f, 0x06], "pmaxud xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x3f, 0x06], "pmaxud xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3f, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x40, 0x06], "pmulld xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x40, 0x06], "pmulld xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x40, 0x06]); - test_instr(&[0x66, 0x0f, 0x38, 0x41, 0x06], "phminposuw xmm0, [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x41, 0x06], "phminposuw xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x41, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x08, 0x06, 0x31], "roundps xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x08, 0x06, 0x31], "roundps xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x08, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x09, 0x06, 0x31], "roundpd xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x09, 0x06, 0x31], "roundpd xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x09, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x0a, 0x06, 0x31], "roundss xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x0a, 0x06, 0x31], "roundss xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x0a, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x0b, 0x06, 0x31], "roundsd xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x0b, 0x06, 0x31], "roundsd xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x0b, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x0e, 0x06, 0x31], "pblendw xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x0e, 0x06, 0x31], "pblendw xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x0e, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x14, 0x06, 0x31], "pextrb xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x14, 0x06, 0x31], "pextrb xmm0, byte [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x14, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x15, 0x06, 0x31], "pextrw xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x15, 0x06, 0x31], "pextrw xmm0, word [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x15, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x16, 0x06, 0x31], "pextrd xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x16, 0x06, 0x31], "pextrd xmm0, dword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x16, 0x06]); - test_instr(&[0x66, 0x48, 0x0f, 0x3a, 0x16, 0x06, 0x31], "pextrq xmm0, [rsi], 0x31"); - test_instr(&[0x66, 0x0f, 0x3a, 0x17, 0x06, 0x31], "extractps xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x48, 0x0f, 0x3a, 0x16, 0x06, 0x31], "pextrq xmm0, qword [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x17, 0x06, 0x31], "extractps xmm0, dword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x17, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x20, 0x06, 0x31], "pinsrb xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x20, 0x06, 0x31], "pinsrb xmm0, byte [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x20, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x21, 0x06, 0x31], "insertps xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x21, 0x06, 0x31], "insertps xmm0, dword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x21, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x22, 0x06, 0x31], "pinsrd xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x22, 0x06, 0x31], "pinsrd xmm0, dword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x22, 0x06]); - test_instr(&[0x66, 0x48, 0x0f, 0x3a, 0x22, 0x06, 0x31], "pinsrq xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x48, 0x0f, 0x3a, 0x22, 0x06, 0x31], "pinsrq xmm0, qword [rsi], 0x31"); - test_instr(&[0x66, 0x0f, 0x3a, 0x40, 0x06, 0x31], "dpps xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x40, 0x06, 0x31], "dpps xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x40, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x41, 0x06, 0x31], "dppd xmm0, [rsi], 0x31"); + test_instr(&[0x66, 0x0f, 0x3a, 0x41, 0x06, 0x31], "dppd xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x41, 0x06]); - test_instr(&[0x66, 0x0f, 0x3a, 0x42, 0x06, 0x44], "mpsadbw xmm0, [rsi], 0x44"); + test_instr(&[0x66, 0x0f, 0x3a, 0x42, 0x06, 0x44], "mpsadbw xmm0, xmmword [rsi], 0x44"); test_invalid(&[0x0f, 0x3a, 0x42, 0x06]); } @@ -802,40 +801,40 @@ fn test_ssse3() { test_invalid_under(&InstDecoder::default(), bytes); } test_instr(&[0x66, 0x0f, 0x38, 0x00, 0xda], "pshufb xmm3, xmm2"); - test_instr(&[0x66, 0x0f, 0x38, 0x00, 0x06], "pshufb xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x00, 0x06], "pshufb mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x01, 0x06], "phaddw xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x01, 0x06], "phaddw mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x02, 0x06], "phaddd xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x02, 0x06], "phaddd mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x03, 0x06], "phaddsw xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x03, 0x06], "phaddsw mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x04, 0x06], "pmaddubsw xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x04, 0x06], "pmaddubsw mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x05, 0x06], "phsubw xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x05, 0x06], "phsubw mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x06, 0x06], "phsubd xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x06, 0x06], "phsubd mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x07, 0x06], "phsubsw xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x07, 0x06], "phsubsw mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x08, 0x06], "psignb xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x08, 0x06], "psignb mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x09, 0x06], "psignw xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x09, 0x06], "psignw mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x0a, 0x06], "psignd xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x0a, 0x06], "psignd mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x0b, 0x06], "pmulhrsw xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x0b, 0x06], "pmulhrsw mm0, [rsi]"); - - test_instr(&[0x66, 0x0f, 0x38, 0x1c, 0x06], "pabsb xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x1c, 0x06], "pabsb mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x1d, 0x06], "pabsw xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x1d, 0x06], "pabsw mm0, [rsi]"); - test_instr(&[0x66, 0x0f, 0x38, 0x1e, 0x06], "pabsd xmm0, [rsi]"); - test_instr(&[0x0f, 0x38, 0x1e, 0x06], "pabsd mm0, [rsi]"); - - test_instr(&[0x66, 0x0f, 0x3a, 0x0f, 0x06, 0x30], "palignr xmm0, [rsi], 0x30"); - test_instr(&[0x0f, 0x3a, 0x0f, 0x06, 0x30], "palignr mm0, [rsi], 0x30"); + test_instr(&[0x66, 0x0f, 0x38, 0x00, 0x06], "pshufb xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x00, 0x06], "pshufb mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x01, 0x06], "phaddw xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x01, 0x06], "phaddw mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x02, 0x06], "phaddd xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x02, 0x06], "phaddd mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x03, 0x06], "phaddsw xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x03, 0x06], "phaddsw mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x04, 0x06], "pmaddubsw xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x04, 0x06], "pmaddubsw mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x05, 0x06], "phsubw xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x05, 0x06], "phsubw mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x06, 0x06], "phsubd xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x06, 0x06], "phsubd mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x07, 0x06], "phsubsw xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x07, 0x06], "phsubsw mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x08, 0x06], "psignb xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x08, 0x06], "psignb mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x09, 0x06], "psignw xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x09, 0x06], "psignw mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x0a, 0x06], "psignd xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x0a, 0x06], "psignd mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x0b, 0x06], "pmulhrsw xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x0b, 0x06], "pmulhrsw mm0, qword [rsi]"); + + test_instr(&[0x66, 0x0f, 0x38, 0x1c, 0x06], "pabsb xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x1c, 0x06], "pabsb mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x1d, 0x06], "pabsw xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x1d, 0x06], "pabsw mm0, qword [rsi]"); + test_instr(&[0x66, 0x0f, 0x38, 0x1e, 0x06], "pabsd xmm0, xmmword [rsi]"); + test_instr(&[0x0f, 0x38, 0x1e, 0x06], "pabsd mm0, qword [rsi]"); + + test_instr(&[0x66, 0x0f, 0x3a, 0x0f, 0x06, 0x30], "palignr xmm0, xmmword [rsi], 0x30"); + test_instr(&[0x0f, 0x3a, 0x0f, 0x06, 0x30], "palignr mm0, qword [rsi], 0x30"); } #[test] @@ -845,17 +844,17 @@ fn test_0f01() { for x in &[0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f] { test_invalid(&[0x0f, 0x01, *x]); } - test_display(&[0x0f, 0x01, 0x38], "invlpg [rax]"); - test_display(&[0x0f, 0x01, 0x3f], "invlpg [rdi]"); - test_display(&[0x0f, 0x01, 0x40, 0xff], "sgdt [rax - 0x1]"); - test_display(&[0x0f, 0x01, 0x41, 0xff], "sgdt [rcx - 0x1]"); - test_display(&[0x0f, 0x01, 0x49, 0xff], "sidt [rcx - 0x1]"); - test_display(&[0x0f, 0x01, 0x51, 0xff], "lgdt [rcx - 0x1]"); - test_display(&[0x0f, 0x01, 0x59, 0xff], "lidt [rcx - 0x1]"); - test_display(&[0x0f, 0x01, 0x61, 0xff], "smsw [rcx - 0x1]"); + test_display(&[0x0f, 0x01, 0x38], "invlpg byte [rax]"); + test_display(&[0x0f, 0x01, 0x3f], "invlpg byte [rdi]"); + test_display(&[0x0f, 0x01, 0x40, 0xff], "sgdt ptr [rax - 0x1]"); + test_display(&[0x0f, 0x01, 0x41, 0xff], "sgdt ptr [rcx - 0x1]"); + test_display(&[0x0f, 0x01, 0x49, 0xff], "sidt ptr [rcx - 0x1]"); + test_display(&[0x0f, 0x01, 0x51, 0xff], "lgdt ptr [rcx - 0x1]"); + test_display(&[0x0f, 0x01, 0x59, 0xff], "lidt ptr [rcx - 0x1]"); + test_display(&[0x0f, 0x01, 0x61, 0xff], "smsw word [rcx - 0x1]"); test_invalid(&[0x0f, 0x01, 0x69, 0xff]); - test_display(&[0x0f, 0x01, 0x71, 0xff], "lmsw [rcx - 0x1]"); - test_display(&[0x0f, 0x01, 0x79, 0xff], "invlpg [rcx - 0x1]"); + test_display(&[0x0f, 0x01, 0x71, 0xff], "lmsw word [rcx - 0x1]"); + test_display(&[0x0f, 0x01, 0x79, 0xff], "invlpg byte [rcx - 0x1]"); test_display(&[0x0f, 0x01, 0xc0], "enclv"); test_display(&[0x0f, 0x01, 0xc1], "vmcall"); test_display(&[0x0f, 0x01, 0xc2], "vmlaunch"); @@ -936,23 +935,23 @@ fn test_0fae() { // Number" test_invalid(&[0xf3, 0x0f, 0xae, 0x87]); test_invalid(&[0xf3, 0x0f, 0xae, 0x04, 0x4f]); - test_display(&[0x0f, 0xae, 0x04, 0x4f], "fxsave [rdi + rcx * 2]"); - test_display(&[0x0f, 0xae, 0x04, 0x4f], "fxsave [rdi + rcx * 2]"); - test_display(&[0x0f, 0xae, 0x0c, 0x4f], "fxrstor [rdi + rcx * 2]"); - test_display(&[0x0f, 0xae, 0x14, 0x4f], "ldmxcsr [rdi + rcx * 2]"); - test_display(&[0x0f, 0xae, 0x1c, 0x4f], "stmxcsr [rdi + rcx * 2]"); - test_display(&[0x0f, 0xae, 0x24, 0x4f], "xsave [rdi + rcx * 2]"); - test_display(&[0x0f, 0xc7, 0x5c, 0x24, 0x40], "xrstors [rsp + 0x40]"); - test_display(&[0x0f, 0xc7, 0x64, 0x24, 0x40], "xsavec [rsp + 0x40]"); - test_display(&[0x0f, 0xc7, 0x6c, 0x24, 0x40], "xsaves [rsp + 0x40]"); - test_display(&[0x4f, 0x0f, 0xc7, 0x5c, 0x24, 0x40], "xrstors64 [r12 + r12 * 1 + 0x40]"); - test_display(&[0x4f, 0x0f, 0xc7, 0x64, 0x24, 0x40], "xsavec64 [r12 + r12 * 1 + 0x40]"); - test_display(&[0x4f, 0x0f, 0xc7, 0x6c, 0x24, 0x40], "xsaves64 [r12 + r12 * 1 + 0x40]"); - test_display(&[0x0f, 0xc7, 0x74, 0x24, 0x40], "vmptrld [rsp + 0x40]"); - test_display(&[0x0f, 0xc7, 0x7c, 0x24, 0x40], "vmptrst [rsp + 0x40]"); - test_display(&[0x0f, 0xae, 0x2c, 0x4f], "xrstor [rdi + rcx * 2]"); - test_display(&[0x0f, 0xae, 0x34, 0x4f], "xsaveopt [rdi + rcx * 2]"); - test_display(&[0x0f, 0xae, 0x3c, 0x4f], "clflush [rdi + rcx * 2]"); + test_display(&[0x0f, 0xae, 0x04, 0x4f], "fxsave ptr [rdi + rcx * 2]"); + test_display(&[0x0f, 0xae, 0x04, 0x4f], "fxsave ptr [rdi + rcx * 2]"); + test_display(&[0x0f, 0xae, 0x0c, 0x4f], "fxrstor ptr [rdi + rcx * 2]"); + test_display(&[0x0f, 0xae, 0x14, 0x4f], "ldmxcsr dword [rdi + rcx * 2]"); + test_display(&[0x0f, 0xae, 0x1c, 0x4f], "stmxcsr dword [rdi + rcx * 2]"); + test_display(&[0x0f, 0xae, 0x24, 0x4f], "xsave ptr [rdi + rcx * 2]"); + test_display(&[0x0f, 0xc7, 0x5c, 0x24, 0x40], "xrstors ptr [rsp + 0x40]"); + test_display(&[0x0f, 0xc7, 0x64, 0x24, 0x40], "xsavec ptr [rsp + 0x40]"); + test_display(&[0x0f, 0xc7, 0x6c, 0x24, 0x40], "xsaves ptr [rsp + 0x40]"); + test_display(&[0x4f, 0x0f, 0xc7, 0x5c, 0x24, 0x40], "xrstors64 ptr [r12 + r12 * 1 + 0x40]"); + test_display(&[0x4f, 0x0f, 0xc7, 0x64, 0x24, 0x40], "xsavec64 ptr [r12 + r12 * 1 + 0x40]"); + test_display(&[0x4f, 0x0f, 0xc7, 0x6c, 0x24, 0x40], "xsaves64 ptr [r12 + r12 * 1 + 0x40]"); + test_display(&[0x0f, 0xc7, 0x74, 0x24, 0x40], "vmptrld qword [rsp + 0x40]"); + test_display(&[0x0f, 0xc7, 0x7c, 0x24, 0x40], "vmptrst qword [rsp + 0x40]"); + test_display(&[0x0f, 0xae, 0x2c, 0x4f], "xrstor ptr [rdi + rcx * 2]"); + test_display(&[0x0f, 0xae, 0x34, 0x4f], "xsaveopt ptr [rdi + rcx * 2]"); + test_display(&[0x0f, 0xae, 0x3c, 0x4f], "clflush zmmword [rdi + rcx * 2]"); for (modrm, text) in &[(0xe8u8, "lfence"), (0xf0u8, "mfence"), (0xf8u8, "sfence")] { test_display_under(&intel, &[0x0f, 0xae, *modrm], text); @@ -979,9 +978,10 @@ fn test_0fae() { #[test] fn test_system() { - test_display(&[0x66, 0x4f, 0x0f, 0xb2, 0x00], "lss r8, [r8]"); - test_display(&[0x67, 0x4f, 0x0f, 0xb2, 0x00], "lss r8, [r8d]"); - test_display(&[0x4f, 0x0f, 0xb2, 0x00], "lss r8, [r8]"); + test_display(&[0x66, 0x4f, 0x0f, 0xb2, 0x00], "lss r8, mword [r8]"); + test_display(&[0x67, 0x4f, 0x0f, 0xb2, 0x00], "lss r8, mword [r8d]"); + test_display(&[0x4f, 0x0f, 0xb2, 0x00], "lss r8, mword [r8]"); + test_display(&[0x0f, 0xb2, 0x00], "lss rax, dword [rax]"); test_invalid(&[0x45, 0x0f, 0x22, 0xc8]); test_invalid(&[0x45, 0x0f, 0x20, 0xc8]); test_display(&[0x40, 0x0f, 0x22, 0xd0], "mov cr2, rax"); @@ -1002,88 +1002,90 @@ fn test_system() { fn test_arithmetic() { test_display(&[0x81, 0xec, 0x10, 0x03, 0x00, 0x00], "sub esp, 0x310"); test_display(&[0x0f, 0xaf, 0xc2], "imul eax, edx"); - test_display(&[0x4b, 0x69, 0x43, 0x6f, 0x6d, 0x70, 0x6c, 0x65], "imul rax, [r11 + 0x6f], 0x656c706d"); + test_display(&[0x4b, 0x69, 0x43, 0x6f, 0x6d, 0x70, 0x6c, 0x65], "imul rax, qword [r11 + 0x6f], 0x656c706d"); test_display(&[0x66, 0x0f, 0xaf, 0xd1], "imul dx, cx"); - test_display(&[0x4b, 0x6b, 0x43, 0x6f, 0x6d], "imul al, [r11 + 0x6f], 0x6d"); + test_display(&[0xf6, 0xe8], "imul al"); + test_display(&[0xf6, 0x28], "imul byte [rax]"); + test_display(&[0x4b, 0x6b, 0x43, 0x6f, 0x6d], "imul rax, qword [r11 + 0x6f], 0x6d"); test_display(&[0x4f, 0x4e, 0x00, 0xcc], "add spl, r9b"); } #[test] #[allow(non_snake_case)] fn test_E_decode() { - test_display(&[0xff, 0x75, 0xb8], "push [rbp - 0x48]"); - test_display(&[0xff, 0x75, 0x08], "push [rbp + 0x8]"); + test_display(&[0xff, 0x75, 0xb8], "push qword [rbp - 0x48]"); + test_display(&[0xff, 0x75, 0x08], "push qword [rbp + 0x8]"); } #[test] fn test_sse() { - test_display(&[0xf3, 0x0f, 0x10, 0x0c, 0xc7], "movss xmm1, [rdi + rax * 8]"); - test_display(&[0xf3, 0x0f, 0x11, 0x0c, 0xc7], "movss [rdi + rax * 8], xmm1"); - test_display(&[0x4f, 0x0f, 0x28, 0x00], "movaps xmm8, [r8]"); - test_display(&[0x4f, 0x0f, 0x29, 0x00], "movaps [r8], xmm8"); + test_display(&[0xf3, 0x0f, 0x10, 0x0c, 0xc7], "movss xmm1, dword [rdi + rax * 8]"); + test_display(&[0xf3, 0x0f, 0x11, 0x0c, 0xc7], "movss dword [rdi + rax * 8], xmm1"); + test_display(&[0x4f, 0x0f, 0x28, 0x00], "movaps xmm8, xmmword [r8]"); + test_display(&[0x4f, 0x0f, 0x29, 0x00], "movaps xmmword [r8], xmm8"); test_display(&[0xf3, 0x4f, 0x0f, 0x2a, 0xc1], "cvtsi2ss xmm8, r9"); - test_display(&[0xf3, 0x4f, 0x0f, 0x2a, 0x01], "cvtsi2ss xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x2b, 0x00], "movntps [r8], xmm8"); + test_display(&[0xf3, 0x4f, 0x0f, 0x2a, 0x01], "cvtsi2ss xmm8, qword [r9]"); + test_display(&[0x4f, 0x0f, 0x2b, 0x00], "movntps xmmword [r8], xmm8"); test_display(&[0xf3, 0x4f, 0x0f, 0x2c, 0xc1], "cvttss2si r8, xmm9"); - test_display(&[0xf3, 0x4f, 0x0f, 0x2c, 0x01], "cvttss2si r8, [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x2c, 0x01], "cvttss2si r8, dword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x2d, 0xc1], "cvtss2si r8, xmm9"); - test_display(&[0xf3, 0x4f, 0x0f, 0x2d, 0x01], "cvtss2si r8, [r9]"); - test_display(&[0x4f, 0x0f, 0x2e, 0x00], "ucomiss xmm8, [r8]"); - test_display(&[0x4f, 0x0f, 0x2f, 0x00], "comiss xmm8, [r8]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x2d, 0x01], "cvtss2si r8, dword [r9]"); + test_display(&[0x4f, 0x0f, 0x2e, 0x00], "ucomiss xmm8, dword [r8]"); + test_display(&[0x4f, 0x0f, 0x2f, 0x00], "comiss xmm8, dword [r8]"); test_display(&[0x0f, 0x28, 0xd0], "movaps xmm2, xmm0"); test_display(&[0x66, 0x0f, 0x28, 0xd0], "movapd xmm2, xmm0"); - test_display(&[0x66, 0x0f, 0x28, 0x00], "movapd xmm0, [rax]"); - test_display(&[0x4f, 0x66, 0x0f, 0x28, 0x00], "movapd xmm0, [rax]"); - test_display(&[0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, [r8]"); - test_display(&[0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, [r8]"); - test_display(&[0x67, 0x4f, 0x66, 0x0f, 0x28, 0x00], "movapd xmm0, [eax]"); - test_display(&[0x67, 0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, [r8d]"); - test_display(&[0x66, 0x0f, 0x29, 0x00], "movapd [rax], xmm0"); + test_display(&[0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [rax]"); + test_display(&[0x4f, 0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [rax]"); + test_display(&[0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, xmmword [r8]"); + test_display(&[0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, xmmword [r8]"); + test_display(&[0x67, 0x4f, 0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [eax]"); + test_display(&[0x67, 0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, xmmword [r8d]"); + test_display(&[0x66, 0x0f, 0x29, 0x00], "movapd xmmword [rax], xmm0"); test_invalid(&[0x4f, 0x0f, 0x50, 0x00]); test_display(&[0x4f, 0x0f, 0x50, 0xc1], "movmskps r8d, xmm9"); - test_display(&[0x4f, 0x0f, 0x51, 0x01], "sqrtps xmm8, [r9]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x51, 0x01], "sqrtss xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x52, 0x01], "rsqrtps xmm8, [r9]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x52, 0x01], "rsqrtss xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x53, 0x01], "rcpps xmm8, [r9]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x53, 0x01], "rcpss xmm8, [r9]"); + test_display(&[0x4f, 0x0f, 0x51, 0x01], "sqrtps xmm8, xmmword [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x51, 0x01], "sqrtss xmm8, dword [r9]"); + test_display(&[0x4f, 0x0f, 0x52, 0x01], "rsqrtps xmm8, xmmword [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x52, 0x01], "rsqrtss xmm8, dword [r9]"); + test_display(&[0x4f, 0x0f, 0x53, 0x01], "rcpps xmm8, xmmword [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x53, 0x01], "rcpss xmm8, dword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x53, 0xc1], "rcpss xmm8, xmm9"); - test_display(&[0x4f, 0x0f, 0x54, 0x01], "andps xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x55, 0x01], "andnps xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x56, 0x01], "orps xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x57, 0x01], "xorps xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x58, 0x01], "addps xmm8, [r9]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x58, 0x01], "addss xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x59, 0x01], "mulps xmm8, [r9]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x59, 0x01], "mulss xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x5a, 0x01], "cvtps2pd xmm8, [r9]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x5a, 0x01], "cvtss2sd xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x5b, 0x01], "cvtdq2ps xmm8, [r9]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x5b, 0x01], "cvttps2dq xmm8, [r9]"); - test_display(&[0x67, 0x4f, 0x0f, 0x5b, 0x01], "cvtdq2ps xmm8, [r9d]"); - test_display(&[0x4f, 0x0f, 0x5c, 0x01], "subps xmm8, [r9]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x5c, 0x01], "subss xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x5d, 0x01], "minps xmm8, [r9]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x5d, 0x01], "minss xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x5e, 0x01], "divps xmm8, [r9]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x5e, 0x01], "divss xmm8, [r9]"); - test_display(&[0x4f, 0x0f, 0x5f, 0x01], "maxps xmm8, [r9]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x5f, 0x01], "maxss xmm8, [r9]"); - - test_display(&[0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, [rax], 0x7f"); - test_display(&[0x4f, 0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, [r8], 0x7f"); + test_display(&[0x4f, 0x0f, 0x54, 0x01], "andps xmm8, xmmword [r9]"); + test_display(&[0x4f, 0x0f, 0x55, 0x01], "andnps xmm8, xmmword [r9]"); + test_display(&[0x4f, 0x0f, 0x56, 0x01], "orps xmm8, xmmword [r9]"); + test_display(&[0x4f, 0x0f, 0x57, 0x01], "xorps xmm8, xmmword [r9]"); + test_display(&[0x4f, 0x0f, 0x58, 0x01], "addps xmm8, xmmword [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x58, 0x01], "addss xmm8, dword [r9]"); + test_display(&[0x4f, 0x0f, 0x59, 0x01], "mulps xmm8, xmmword [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x59, 0x01], "mulss xmm8, dword [r9]"); + test_display(&[0x4f, 0x0f, 0x5a, 0x01], "cvtps2pd xmm8, qword [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x5a, 0x01], "cvtss2sd xmm8, qword [r9]"); + test_display(&[0x4f, 0x0f, 0x5b, 0x01], "cvtdq2ps xmm8, xmmword [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x5b, 0x01], "cvttps2dq xmm8, xmmword [r9]"); + test_display(&[0x67, 0x4f, 0x0f, 0x5b, 0x01], "cvtdq2ps xmm8, xmmword [r9d]"); + test_display(&[0x4f, 0x0f, 0x5c, 0x01], "subps xmm8, xmmword [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x5c, 0x01], "subss xmm8, dword [r9]"); + test_display(&[0x4f, 0x0f, 0x5d, 0x01], "minps xmm8, xmmword [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x5d, 0x01], "minss xmm8, dword [r9]"); + test_display(&[0x4f, 0x0f, 0x5e, 0x01], "divps xmm8, xmmword [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x5e, 0x01], "divss xmm8, dword [r9]"); + test_display(&[0x4f, 0x0f, 0x5f, 0x01], "maxps xmm8, xmmword [r9]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x5f, 0x01], "maxss xmm8, dword [r9]"); + + test_display(&[0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [rax], 0x7f"); + test_display(&[0x4f, 0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [r8], 0x7f"); test_display(&[0x66, 0x0f, 0xef, 0xc0], "pxor xmm0, xmm0"); test_display(&[0x66, 0x4f, 0x0f, 0xef, 0xc0], "pxor xmm8, xmm8"); - test_display(&[0xf2, 0x0f, 0x10, 0x0c, 0xc6], "movsd xmm1, [rsi + rax * 8]"); - test_display(&[0xf3, 0x0f, 0x10, 0x04, 0x86], "movss xmm0, [rsi + rax * 4]"); + test_display(&[0xf2, 0x0f, 0x10, 0x0c, 0xc6], "movsd xmm1, qword [rsi + rax * 8]"); + test_display(&[0xf3, 0x0f, 0x10, 0x04, 0x86], "movss xmm0, dword [rsi + rax * 4]"); test_display(&[0xf2, 0x0f, 0x59, 0xc8], "mulsd xmm1, xmm0"); test_display(&[0xf3, 0x0f, 0x59, 0xc8], "mulss xmm1, xmm0"); test_display(&[0xf2, 0x4f, 0x0f, 0x59, 0xc8], "mulsd xmm9, xmm8"); test_display( &[0xf3, 0x4f, 0x0f, 0x6f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "movdqu xmm11, [r12 + r11 * 4 - 0x334455cc]" + "movdqu xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_display(&[0xf3, 0x0f, 0x70, 0xc0, 0x4e], "pshufhw xmm0, xmm0, 0x4e"); test_display(&[0xf3, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm1"); @@ -1095,58 +1097,58 @@ fn test_sse() { test_display(&[0xf3, 0x48, 0x0f, 0x7e, 0xc1], "movd rcx, mm0"); test_display( &[0xf3, 0x4f, 0x0f, 0x7f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], - "movdqu [r12 + r11 * 4 - 0x334455cc], xmm11" + "movdqu xmmword [r12 + r11 * 4 - 0x334455cc], xmm11" ); test_display(&[0xf3, 0x0f, 0xc2, 0xc3, 0x08], "cmpss xmm0, xmm3, 0x8"); test_display(&[0xf3, 0x4f, 0x0f, 0xc2, 0xc3, 0x08], "cmpss xmm8, xmm11, 0x8"); - test_display(&[0xf3, 0x4f, 0x0f, 0xc2, 0x03, 0x08], "cmpss xmm8, [r11], 0x8"); + test_display(&[0xf3, 0x4f, 0x0f, 0xc2, 0x03, 0x08], "cmpss xmm8, dword [r11], 0x8"); } // SETLE, SETNG, ... #[test] fn test_mov() { - test_display(&[0xa0, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov al, [0x3412341200c46293]"); - test_display(&[0x67, 0xa0, 0x93, 0x62, 0xc4, 0x00], "mov al, [0xc46293]"); - test_display(&[0xa1, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov eax, [0x3412341200c46293]"); - test_display(&[0x67, 0xa1, 0x93, 0x62, 0xc4, 0x00], "mov eax, [0xc46293]"); - test_display(&[0xa2, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov [0x3412341200c46293], al"); - test_display(&[0x67, 0xa2, 0x93, 0x62, 0xc4, 0x00], "mov [0xc46293], al"); - test_display(&[0xa3, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov [0x3412341200c46293], eax"); - test_display(&[0x67, 0xa3, 0x93, 0x62, 0xc4, 0x00], "mov [0xc46293], eax"); + test_display(&[0xa0, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov al, byte [0x3412341200c46293]"); + test_display(&[0x67, 0xa0, 0x93, 0x62, 0xc4, 0x00], "mov al, byte [0xc46293]"); + test_display(&[0xa1, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov eax, dword [0x3412341200c46293]"); + test_display(&[0x67, 0xa1, 0x93, 0x62, 0xc4, 0x00], "mov eax, dword [0xc46293]"); + test_display(&[0xa2, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov byte [0x3412341200c46293], al"); + test_display(&[0x67, 0xa2, 0x93, 0x62, 0xc4, 0x00], "mov byte [0xc46293], al"); + test_display(&[0xa3, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov dword [0x3412341200c46293], eax"); + test_display(&[0x67, 0xa3, 0x93, 0x62, 0xc4, 0x00], "mov dword [0xc46293], eax"); test_display(&[0xba, 0x01, 0x00, 0x00, 0x00], "mov edx, 0x1"); - test_display(&[0x48, 0xc7, 0x04, 0x24, 0x00, 0x00, 0x00, 0x00], "mov [rsp], 0x0"); - test_display(&[0x48, 0x89, 0x44, 0x24, 0x08], "mov [rsp + 0x8], rax"); - test_display(&[0x48, 0x89, 0x43, 0x18], "mov [rbx + 0x18], rax"); - test_display(&[0x48, 0xc7, 0x43, 0x10, 0x00, 0x00, 0x00, 0x00], "mov [rbx + 0x10], 0x0"); - test_display(&[0x49, 0x89, 0x4e, 0x08], "mov [r14 + 0x8], rcx"); - test_display(&[0x48, 0x8b, 0x32], "mov rsi, [rdx]"); - test_display(&[0x4d, 0x8b, 0x4c, 0x10, 0xf8], "mov r9, [r8 + rdx * 1 - 0x8]"); - test_display(&[0x49, 0x89, 0x46, 0x10], "mov [r14 + 0x10], rax"); + test_display(&[0x48, 0xc7, 0x04, 0x24, 0x00, 0x00, 0x00, 0x00], "mov qword [rsp], 0x0"); + test_display(&[0x48, 0x89, 0x44, 0x24, 0x08], "mov qword [rsp + 0x8], rax"); + test_display(&[0x48, 0x89, 0x43, 0x18], "mov qword [rbx + 0x18], rax"); + test_display(&[0x48, 0xc7, 0x43, 0x10, 0x00, 0x00, 0x00, 0x00], "mov qword [rbx + 0x10], 0x0"); + test_display(&[0x49, 0x89, 0x4e, 0x08], "mov qword [r14 + 0x8], rcx"); + test_display(&[0x48, 0x8b, 0x32], "mov rsi, qword [rdx]"); + test_display(&[0x4d, 0x8b, 0x4c, 0x10, 0xf8], "mov r9, qword [r8 + rdx * 1 - 0x8]"); + test_display(&[0x49, 0x89, 0x46, 0x10], "mov qword [r14 + 0x10], rax"); test_display(&[0x4d, 0x0f, 0x43, 0xec], "cmovnb r13, r12"); test_display(&[0x0f, 0xb6, 0x06], "movzx eax, byte [rsi]"); test_display(&[0x0f, 0xb7, 0x06], "movzx eax, word [rsi]"); - test_display(&[0x89, 0x55, 0x94], "mov [rbp - 0x6c], edx"); - test_display(&[0x65, 0x4c, 0x89, 0x04, 0x25, 0xa8, 0x01, 0x00, 0x00], "mov gs:[0x1a8], r8"); + test_display(&[0x89, 0x55, 0x94], "mov dword [rbp - 0x6c], edx"); + test_display(&[0x65, 0x4c, 0x89, 0x04, 0x25, 0xa8, 0x01, 0x00, 0x00], "mov qword gs:[0x1a8], r8"); test_display(&[0x0f, 0xbe, 0x83, 0xb4, 0x00, 0x00, 0x00], "movsx eax, byte [rbx + 0xb4]"); test_display(&[0x46, 0x63, 0xc1], "movsxd r8, ecx"); - test_display(&[0x48, 0x63, 0x04, 0xba], "movsxd rax, [rdx + rdi * 4]"); - test_display(&[0xf3, 0x0f, 0x6f, 0x07], "movdqu xmm0, [rdi]"); - test_display(&[0xf3, 0x0f, 0x7f, 0x45, 0x00], "movdqu [rbp], xmm0"); + test_display(&[0x48, 0x63, 0x04, 0xba], "movsxd rax, dword [rdx + rdi * 4]"); + test_display(&[0xf3, 0x0f, 0x6f, 0x07], "movdqu xmm0, xmmword [rdi]"); + test_display(&[0xf3, 0x0f, 0x7f, 0x45, 0x00], "movdqu xmmword [rbp], xmm0"); test_display(&[0x0f, 0x97, 0xc0], "seta al"); test_display(&[0x0f, 0x97, 0xc8], "seta al"); - test_display(&[0x0f, 0x97, 0x00], "seta [rax]"); - test_display(&[0x0f, 0x97, 0x08], "seta [rax]"); + test_display(&[0x0f, 0x97, 0x00], "seta byte [rax]"); + test_display(&[0x0f, 0x97, 0x08], "seta byte [rax]"); // test_display(&[0xd6], "salc"); - test_display(&[0x8e, 0x00], "mov es, [rax]"); + test_display(&[0x8e, 0x00], "mov es, word [rax]"); // cs is not an allowed destination test_invalid(&[0x8e, 0x08]); - test_display(&[0x8e, 0x10], "mov ss, [rax]"); - test_display(&[0x8e, 0x18], "mov ds, [rax]"); - test_display(&[0x8e, 0x20], "mov fs, [rax]"); - test_display(&[0x8e, 0x28], "mov gs, [rax]"); + test_display(&[0x8e, 0x10], "mov ss, word [rax]"); + test_display(&[0x8e, 0x18], "mov ds, word [rax]"); + test_display(&[0x8e, 0x20], "mov fs, word [rax]"); + test_display(&[0x8e, 0x28], "mov gs, word [rax]"); test_invalid(&[0x8e, 0x30]); test_invalid(&[0x8e, 0x38]); } @@ -1170,10 +1172,10 @@ fn test_prefixes() { test_display(&[0x66, 0x41, 0x32, 0xc0], "xor al, r8b"); test_display(&[0x40, 0x32, 0xc5], "xor al, bpl"); test_invalid(&[0xf0, 0x33, 0xc0]); - test_display(&[0xf0, 0x31, 0x00], "lock xor [rax], eax"); - test_display(&[0xf0, 0x80, 0x30, 0x00], "lock xor [rax], 0x0"); - test_display(&[0xf0, 0x0f, 0xbb, 0x17], "lock btc [rdi], edx"); - test_display(&[0x66, 0x2e, 0xf2, 0xf0, 0x0f, 0xbb, 0x13], "lock btc [rbx], dx"); + test_display(&[0xf0, 0x31, 0x00], "lock xor dword [rax], eax"); + test_display(&[0xf0, 0x80, 0x30, 0x00], "lock xor byte [rax], 0x0"); + test_display(&[0xf0, 0x0f, 0xbb, 0x17], "lock btc dword [rdi], edx"); + test_display(&[0x66, 0x2e, 0xf2, 0xf0, 0x0f, 0xbb, 0x13], "lock btc word [rbx], dx"); test_invalid(&[0xf0, 0xc7, 0x00, 0x00, 0x00, 0x00]); test_display(&[0x0f, 0xc1, 0xcc], "xadd esp, ecx"); test_display(&[0x66, 0x0f, 0xc1, 0xcc], "xadd sp, cx"); @@ -1191,13 +1193,13 @@ fn test_control_flow() { test_display(&[0x72, 0x5a], "jb 0x5a"); test_display(&[0x0f, 0x86, 0x8b, 0x01, 0x00, 0x00], "jna 0x18b"); test_display(&[0x74, 0x47], "jz 0x47"); - test_display(&[0xff, 0x15, 0x7e, 0x72, 0x24, 0x00], "call [rip + 0x24727e]"); - test_display(&[0xff, 0x24, 0xcd, 0x70, 0xa0, 0xbc, 0x01], "jmp [rcx * 8 + 0x1bca070]"); + test_display(&[0xff, 0x15, 0x7e, 0x72, 0x24, 0x00], "call qword [rip + 0x24727e]"); + test_display(&[0xff, 0x24, 0xcd, 0x70, 0xa0, 0xbc, 0x01], "jmp qword [rcx * 8 + 0x1bca070]"); test_display(&[0xff, 0xe0], "jmp rax"); test_display(&[0x66, 0xff, 0xe0], "jmp rax"); test_display(&[0x67, 0xff, 0xe0], "jmp rax"); test_invalid(&[0xff, 0xd8]); - test_display(&[0xff, 0x18], "callf [rax]"); + test_display(&[0xff, 0x18], "callf far [rax]"); test_display(&[0xe0, 0x12], "loopnz 0x12"); test_display(&[0xe1, 0x12], "loopz 0x12"); test_display(&[0xe2, 0x12], "loop 0x12"); @@ -1219,7 +1221,7 @@ fn bad_instructions() { #[test] fn test_test_cmp() { - test_display(&[0xf6, 0x05, 0x2c, 0x9b, 0xff, 0xff, 0x01], "test [rip - 0x64d4], 0x1"); + test_display(&[0xf6, 0x05, 0x2c, 0x9b, 0xff, 0xff, 0x01], "test byte [rip - 0x64d4], 0x1"); test_display(&[0x48, 0x3d, 0x01, 0xf0, 0xff, 0xff], "cmp rax, -0xfff"); test_display(&[0x3d, 0x01, 0xf0, 0xff, 0xff], "cmp eax, -0xfff"); test_display(&[0x48, 0x83, 0xf8, 0xff], "cmp rax, -0x1"); @@ -1231,8 +1233,9 @@ fn test_push_pop() { test_display(&[0x5b], "pop rbx"); test_display(&[0x41, 0x5e], "pop r14"); test_display(&[0x68, 0x7f, 0x63, 0xc4, 0x00], "push 0xc4637f"); - test_display(&[0x66, 0x8f, 0x00], "pop [rax]"); - test_display(&[0x8f, 0x00], "pop [rax]"); + test_display(&[0x66, 0x8f, 0x00], "pop word [rax]"); + test_display(&[0x8f, 0x00], "pop qword [rax]"); + test_display(&[0x48, 0x8f, 0x00], "pop qword [rax]"); } #[test] @@ -1245,46 +1248,46 @@ fn test_bmi1() { test_display_under(&no_bmi1, &[0xf3, 0x41, 0x0f, 0xbc, 0xd3], "bsf edx, r11d"); // just 0f38 - test_display_under(&bmi1, &[0xc4, 0xc2, 0x60, 0xf2, 0x01], "andn eax, ebx, [r9]"); - test_display_under(&bmi1, &[0xc4, 0xc2, 0xe0, 0xf2, 0x01], "andn rax, rbx, [r9]"); - test_display_under(&bmi1, &[0xc4, 0xc2, 0x78, 0xf3, 0x09], "blsr eax, [r9]"); - test_display_under(&bmi1, &[0xc4, 0xc2, 0xf8, 0xf3, 0x09], "blsr rax, [r9]"); - test_display_under(&bmi1, &[0xc4, 0xc2, 0x78, 0xf3, 0x11], "blsmsk eax, [r9]"); - test_display_under(&bmi1, &[0xc4, 0xc2, 0xf8, 0xf3, 0x11], "blsmsk rax, [r9]"); - test_display_under(&bmi1, &[0xc4, 0xc2, 0x78, 0xf3, 0x19], "blsi eax, [r9]"); - test_display_under(&bmi1, &[0xc4, 0xc2, 0xf8, 0xf3, 0x19], "blsi rax, [r9]"); - test_display_under(&bmi1, &[0xc4, 0xc2, 0x60, 0xf7, 0x01], "bextr eax, [r9], ebx"); - test_display_under(&bmi1, &[0xc4, 0xc2, 0xe0, 0xf7, 0x01], "bextr rax, [r9], rbx"); + test_display_under(&bmi1, &[0xc4, 0xc2, 0x60, 0xf2, 0x01], "andn eax, ebx, dword [r9]"); + test_display_under(&bmi1, &[0xc4, 0xc2, 0xe0, 0xf2, 0x01], "andn rax, rbx, qword [r9]"); + test_display_under(&bmi1, &[0xc4, 0xc2, 0x78, 0xf3, 0x09], "blsr eax, dword [r9]"); + test_display_under(&bmi1, &[0xc4, 0xc2, 0xf8, 0xf3, 0x09], "blsr rax, qword [r9]"); + test_display_under(&bmi1, &[0xc4, 0xc2, 0x78, 0xf3, 0x11], "blsmsk eax, dword [r9]"); + test_display_under(&bmi1, &[0xc4, 0xc2, 0xf8, 0xf3, 0x11], "blsmsk rax, qword [r9]"); + test_display_under(&bmi1, &[0xc4, 0xc2, 0x78, 0xf3, 0x19], "blsi eax, dword [r9]"); + test_display_under(&bmi1, &[0xc4, 0xc2, 0xf8, 0xf3, 0x19], "blsi rax, qword [r9]"); + test_display_under(&bmi1, &[0xc4, 0xc2, 0x60, 0xf7, 0x01], "bextr eax, dword [r9], ebx"); + test_display_under(&bmi1, &[0xc4, 0xc2, 0xe0, 0xf7, 0x01], "bextr rax, qword [r9], rbx"); } #[test] fn test_bmi2() { let bmi2 = InstDecoder::minimal().with_bmi2(); // f2 0f3a - test_display_under(&bmi2, &[0xc4, 0xc3, 0x7b, 0xf0, 0x01, 0x05], "rorx eax, [r9], 0x5"); - test_display_under(&bmi2, &[0xc4, 0xc3, 0xfb, 0xf0, 0x01, 0x05], "rorx rax, [r9], 0x5"); + test_display_under(&bmi2, &[0xc4, 0xc3, 0x7b, 0xf0, 0x01, 0x05], "rorx eax, dword [r9], 0x5"); + test_display_under(&bmi2, &[0xc4, 0xc3, 0xfb, 0xf0, 0x01, 0x05], "rorx rax, qword [r9], 0x5"); // f2 0f38 map - test_display_under(&bmi2, &[0xc4, 0xe2, 0x63, 0xf5, 0x07], "pdep eax, ebx, [rdi]"); - test_display_under(&bmi2, &[0xc4, 0xe2, 0xe3, 0xf5, 0x07], "pdep rax, rbx, [rdi]"); - test_display_under(&bmi2, &[0xc4, 0xe2, 0x63, 0xf6, 0x07], "mulx eax, ebx, [rdi]"); - test_display_under(&bmi2, &[0xc4, 0xe2, 0xe3, 0xf6, 0x07], "mulx rax, rbx, [rdi]"); - test_display_under(&bmi2, &[0xc4, 0xc2, 0x63, 0xf7, 0x01], "shrx eax, [r9], ebx"); - test_display_under(&bmi2, &[0xc4, 0xc2, 0xe3, 0xf7, 0x01], "shrx rax, [r9], rbx"); + test_display_under(&bmi2, &[0xc4, 0xe2, 0x63, 0xf5, 0x07], "pdep eax, ebx, dword [rdi]"); + test_display_under(&bmi2, &[0xc4, 0xe2, 0xe3, 0xf5, 0x07], "pdep rax, rbx, qword [rdi]"); + test_display_under(&bmi2, &[0xc4, 0xe2, 0x63, 0xf6, 0x07], "mulx eax, ebx, dword [rdi]"); + test_display_under(&bmi2, &[0xc4, 0xe2, 0xe3, 0xf6, 0x07], "mulx rax, rbx, qword [rdi]"); + test_display_under(&bmi2, &[0xc4, 0xc2, 0x63, 0xf7, 0x01], "shrx eax, dword [r9], ebx"); + test_display_under(&bmi2, &[0xc4, 0xc2, 0xe3, 0xf7, 0x01], "shrx rax, qword [r9], rbx"); // f3 0f38 map - test_display_under(&bmi2, &[0xc4, 0xe2, 0x62, 0xf5, 0x07], "pext eax, ebx, [rdi]"); - test_display_under(&bmi2, &[0xc4, 0xe2, 0xe2, 0xf5, 0x07], "pext rax, rbx, [rdi]"); - test_display_under(&bmi2, &[0xc4, 0xc2, 0x62, 0xf7, 0x01], "sarx eax, [r9], ebx"); - test_display_under(&bmi2, &[0xc4, 0xc2, 0xe2, 0xf7, 0x01], "sarx rax, [r9], rbx"); + test_display_under(&bmi2, &[0xc4, 0xe2, 0x62, 0xf5, 0x07], "pext eax, ebx, dword [rdi]"); + test_display_under(&bmi2, &[0xc4, 0xe2, 0xe2, 0xf5, 0x07], "pext rax, rbx, qword [rdi]"); + test_display_under(&bmi2, &[0xc4, 0xc2, 0x62, 0xf7, 0x01], "sarx eax, dword [r9], ebx"); + test_display_under(&bmi2, &[0xc4, 0xc2, 0xe2, 0xf7, 0x01], "sarx rax, qword [r9], rbx"); // just 0f38 - test_display_under(&bmi2, &[0xc4, 0xe2, 0x60, 0xf5, 0x07], "bzhi eax, [rdi], ebx"); - test_display_under(&bmi2, &[0xc4, 0xe2, 0xe0, 0xf5, 0x07], "bzhi rax, [rdi], rbx"); + test_display_under(&bmi2, &[0xc4, 0xe2, 0x60, 0xf5, 0x07], "bzhi eax, dword [rdi], ebx"); + test_display_under(&bmi2, &[0xc4, 0xe2, 0xe0, 0xf5, 0x07], "bzhi rax, qword [rdi], rbx"); // 66 0f38 - test_display_under(&bmi2, &[0xc4, 0xc2, 0x61, 0xf7, 0x01], "shlx eax, [r9], ebx"); - test_display_under(&bmi2, &[0xc4, 0xc2, 0xe1, 0xf7, 0x01], "shlx rax, [r9], rbx"); + test_display_under(&bmi2, &[0xc4, 0xc2, 0x61, 0xf7, 0x01], "shlx eax, dword [r9], ebx"); + test_display_under(&bmi2, &[0xc4, 0xc2, 0xe1, 0xf7, 0x01], "shlx rax, qword [r9], rbx"); } #[test] @@ -1302,8 +1305,8 @@ fn test_popcnt() { #[test] fn test_bitwise() { test_display_under(&InstDecoder::minimal(), &[0x41, 0x0f, 0xbc, 0xd3], "bsf edx, r11d"); - test_display_under(&InstDecoder::minimal(), &[0x0f, 0xbb, 0x17], "btc [rdi], edx"); - test_display_under(&InstDecoder::minimal(), &[0xf0, 0x0f, 0xbb, 0x17], "lock btc [rdi], edx"); + test_display_under(&InstDecoder::minimal(), &[0x0f, 0xbb, 0x17], "btc dword [rdi], edx"); + test_display_under(&InstDecoder::minimal(), &[0xf0, 0x0f, 0xbb, 0x17], "lock btc dword [rdi], edx"); test_display(&[0x48, 0x0f, 0xa3, 0xd0], "bt rax, rdx"); test_display(&[0x48, 0x0f, 0xab, 0xd0], "bts rax, rdx"); test_display(&[0x48, 0x0f, 0xb3, 0xd0], "btr rax, rdx"); @@ -1326,10 +1329,10 @@ fn test_misc() { test_display(&[0x66, 0x4f, 0xcf], "iretq"); test_display(&[0xf2, 0x0f, 0x38, 0xf0, 0xc1], "crc32 eax, cl"); test_display(&[0xf2, 0x0f, 0x38, 0xf1, 0xc1], "crc32 eax, ecx"); - test_display(&[0xfe, 0x00], "inc [rax]"); // TODO: inc byte [rax] - test_display(&[0xfe, 0x08], "dec [rax]"); // TODO: dec byte [rax] - test_display(&[0xff, 0x00], "inc [rax]"); // TODO: inc dword [rax] - test_display(&[0x48, 0xff, 0x00], "inc [rax]"); // TODO: inc qword [rax] + test_display(&[0xfe, 0x00], "inc byte [rax]"); + test_display(&[0xfe, 0x08], "dec byte [rax]"); + test_display(&[0xff, 0x00], "inc dword [rax]"); + test_display(&[0x48, 0xff, 0x00], "inc qword [rax]"); test_display(&[0xe4, 0x99], "in al, 0x99"); test_display(&[0xe5, 0x99], "in eax, 0x99"); test_display(&[0x67, 0xe5, 0x99], "in eax, 0x99"); @@ -1346,25 +1349,25 @@ fn test_misc() { test_display(&[0x48, 0x98], "cdqe"); test_display(&[0x98], "cwde"); test_display(&[0x66, 0x99], "cwd"); - test_display(&[0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00], "nop [rax + rax * 1]"); - test_display(&[0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00], "nop [rax + rax * 1]"); - test_display(&[0x48, 0x8d, 0xa4, 0xc7, 0x20, 0x00, 0x00, 0x12], "lea rsp, [rdi + rax * 8 + 0x12000020]"); + test_display(&[0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00], "nop word [rax + rax * 1]"); + test_display(&[0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00], "nop word [rax + rax * 1]"); + test_display(&[0x48, 0x8d, 0xa4, 0xc7, 0x20, 0x00, 0x00, 0x12], "lea rsp, qword [rdi + rax * 8 + 0x12000020]"); test_display(&[0x33, 0xc0], "xor eax, eax"); - test_display(&[0x48, 0x8d, 0x53, 0x08], "lea rdx, [rbx + 0x8]"); + test_display(&[0x48, 0x8d, 0x53, 0x08], "lea rdx, qword [rbx + 0x8]"); test_invalid(&[0x8d, 0xdd]); test_display(&[0x31, 0xc9], "xor ecx, ecx"); test_display(&[0x48, 0x29, 0xc8], "sub rax, rcx"); - test_display(&[0x48, 0x03, 0x0b], "add rcx, [rbx]"); - test_display(&[0x48, 0x8d, 0x0c, 0x12], "lea rcx, [rdx + rdx * 1]"); + test_display(&[0x48, 0x03, 0x0b], "add rcx, qword [rbx]"); + test_display(&[0x48, 0x8d, 0x0c, 0x12], "lea rcx, qword [rdx + rdx * 1]"); test_display(&[0xf6, 0xc2, 0x18], "test dl, 0x18"); - test_display(&[0xf3, 0x48, 0xab], "rep stos es:[rdi], rax"); - test_display(&[0xf3, 0x48, 0xa5], "rep movs es:[rdi], ds:[rsi]"); + test_display(&[0xf3, 0x48, 0xab], "rep stos qword es:[rdi], rax"); + test_display(&[0xf3, 0x48, 0xa5], "rep movs qword es:[rdi], qword ds:[rsi]"); test_display(&[0xf3, 0x45, 0x0f, 0xbc, 0xd7], "tzcnt r10d, r15d"); - test_display(&[0xf3, 0x0f, 0xae, 0x26], "ptwrite [rsi]"); + test_display(&[0xf3, 0x0f, 0xae, 0x26], "ptwrite dword [rsi]"); test_display(&[0xf3, 0x0f, 0xae, 0xe6], "ptwrite esi"); test_invalid(&[0x66, 0xf3, 0x0f, 0xae, 0xe6]); - test_display(&[0xf3, 0x49, 0x0f, 0xae, 0x26], "ptwrite [r14]"); + test_display(&[0xf3, 0x49, 0x0f, 0xae, 0x26], "ptwrite qword [r14]"); test_display(&[0xf3, 0x0f, 0xae, 0xc4], "rdfsbase esp"); test_display(&[0xf3, 0x4f, 0x0f, 0xae, 0xc4], "rdfsbase r12"); test_display(&[0xf3, 0x0f, 0xae, 0xcc], "rdgsbase esp"); @@ -1373,23 +1376,24 @@ fn test_misc() { test_display(&[0xf3, 0x4f, 0x0f, 0xae, 0xd4], "wrfsbase r12"); test_display(&[0xf3, 0x0f, 0xae, 0xdc], "wrgsbase esp"); test_display(&[0xf3, 0x4f, 0x0f, 0xae, 0xdc], "wrgsbase r12"); - test_display(&[0x66, 0x0f, 0xae, 0x3f], "clflushopt [rdi]"); // or clflush without 66 + test_display(&[0x66, 0x0f, 0xae, 0x3f], "clflushopt zmmword [rdi]"); + test_display(&[0x0f, 0xae, 0x3f], "clflush zmmword [rdi]"); test_invalid(&[0x66, 0x0f, 0xae, 0xff]); - test_display(&[0x66, 0x0f, 0xae, 0x37], "clwb [rdi]"); + test_display(&[0x66, 0x0f, 0xae, 0x37], "clwb zmmword [rdi]"); test_display(&[0x66, 0x0f, 0xae, 0xf7], "tpause edi"); test_display(&[0xf3, 0x0f, 0xae, 0xf1], "umonitor rcx"); test_display(&[0xf2, 0x0f, 0xae, 0xf1], "umwait ecx"); test_display(&[0xf2, 0x4f, 0x0f, 0xae, 0xf1], "umwait r9"); - test_display(&[0x66, 0x0f, 0x38, 0x80, 0x2f], "invept ebp, [rdi]"); - test_display(&[0x66, 0x49, 0x0f, 0x38, 0x80, 0x2f], "invept rbp, [r15]"); + test_display(&[0x66, 0x0f, 0x38, 0x80, 0x2f], "invept rbp, xmmword [rdi]"); + test_display(&[0x66, 0x49, 0x0f, 0x38, 0x80, 0x2f], "invept rbp, xmmword [r15]"); test_invalid(&[0x0f, 0x38, 0x80, 0x2f]); test_invalid(&[0x43, 0x0f, 0x38, 0x80, 0x2f]); - test_display(&[0x66, 0x0f, 0x38, 0x81, 0x2f], "invvpid ebp, [rdi]"); - test_display(&[0x66, 0x49, 0x0f, 0x38, 0x81, 0x2f], "invvpid rbp, [r15]"); + test_display(&[0x66, 0x0f, 0x38, 0x81, 0x2f], "invvpid rbp, xmmword [rdi]"); + test_display(&[0x66, 0x49, 0x0f, 0x38, 0x81, 0x2f], "invvpid rbp, xmmword [r15]"); test_invalid(&[0x0f, 0x38, 0x81, 0x2f]); test_invalid(&[0x43, 0x0f, 0x38, 0x81, 0x2f]); - test_display(&[0x66, 0x0f, 0x38, 0x82, 0x2f], "invpcid ebp, [rdi]"); - test_display(&[0x66, 0x49, 0x0f, 0x38, 0x82, 0x2f], "invpcid rbp, [r15]"); + test_display(&[0x66, 0x0f, 0x38, 0x82, 0x2f], "invpcid rbp, xmmword [rdi]"); + test_display(&[0x66, 0x49, 0x0f, 0x38, 0x82, 0x2f], "invpcid rbp, xmmword [r15]"); test_invalid(&[0x0f, 0x38, 0x82, 0x2f]); test_invalid(&[0x43, 0x0f, 0x38, 0x82, 0x2f]); test_display(&[0x66, 0x0f, 0xae, 0xf1], "tpause ecx"); @@ -1438,11 +1442,9 @@ fn test_vex() { test_invalid(&[0xc4, 0b000_00011, 0b1_1111_001, 0x02, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b1_1111_101, 0x02, 0b11_001_010, 0x77]); test_avx2(&[0xc4, 0b000_00011, 0b0_1111_001, 0x02, 0b11_001_010, 0x77], "vpblendd xmm9, xmm0, xmm10, 0x77"); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00011, 0b0_1111_001, 0x02, 0b00_001_010, 0x77], "vpblendd xmm9, xmm0, [r10], 0x77"); + test_avx2(&[0xc4, 0b000_00011, 0b0_1111_001, 0x02, 0b00_001_010, 0x77], "vpblendd xmm9, xmm0, xmmword [r10], 0x77"); test_avx2(&[0xc4, 0b000_00011, 0b0_1111_101, 0x02, 0b11_001_010, 0x77], "vpblendd ymm9, ymm0, ymm10, 0x77"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00011, 0b0_1111_101, 0x02, 0b00_001_010, 0x77], "vpblendd ymm9, ymm0, [r10], 0x77"); + test_avx2(&[0xc4, 0b000_00011, 0b0_1111_101, 0x02, 0b00_001_010, 0x77], "vpblendd ymm9, ymm0, ymmword [r10], 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x04, 0b11_001_010, 0x77], "vpermilps xmm9, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x04, 0b11_001_010, 0x77], "vpermilps ymm9, ymm10, 0x77"); @@ -1450,8 +1452,7 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x05, 0b11_001_010, 0x77], "vpermilpd ymm9, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_001, 0x06, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x06, 0b11_001_010, 0x77], "vperm2f128 ymm9, ymm0, ymm10, 0x77"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x06, 0b00_001_010, 0x77], "vperm2f128 ymm9, ymm0, [r10], 0x77"); + test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x06, 0b00_001_010, 0x77], "vperm2f128 ymm9, ymm0, ymmword [r10], 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x0c, 0b11_001_010, 0x77], "vblendps xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_101, 0x0c, 0b11_001_010, 0x77], "vblendps ymm9, ymm8, ymm10, 0x77"); @@ -1477,22 +1478,22 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00011, 0b1_0111_101, 0x0f, 0b11_001_010, 0x77], "vpalignr ymm9, ymm8, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x14, 0b11_001_010, 0x77], "vpextrb r10d, xmm9, 0x77"); - test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x14, 0b00_001_010, 0x77], "vpextrb [r10], xmm9, 0x77"); + test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x14, 0b00_001_010, 0x77], "vpextrb byte [r10], xmm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x14, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x14, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x15, 0b11_001_010, 0x77], "vpextrw r10d, xmm9, 0x77"); - test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x15, 0b00_001_010, 0x77], "vpextrw [r10], xmm9, 0x77"); + test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x15, 0b00_001_010, 0x77], "vpextrw word [r10], xmm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x15, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x15, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x16, 0b11_001_010, 0x77], "vpextrd r10d, xmm9, 0x77"); - test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x16, 0b00_001_010, 0x77], "vpextrd [r10], xmm9, 0x77"); + test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x16, 0b00_001_010, 0x77], "vpextrd dword [r10], xmm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x16, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x16, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b1_1111_001, 0x16, 0b11_001_010, 0x77], "vpextrq r10, xmm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_001, 0x16, 0b00_001_010, 0x77]); - test_instr(&[0xc4, 0b000_00011, 0b1_1111_001, 0x16, 0b00_001_010, 0x77], "vpextrq [r10], xmm9, 0x77"); + test_instr(&[0xc4, 0b000_00011, 0b1_1111_001, 0x16, 0b00_001_010, 0x77], "vpextrq qword [r10], xmm9, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x17, 0b11_001_010, 0x77], "vextractps r10d, xmm9, 0x77"); - test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x17, 0b00_001_010, 0x77], "vextractps [r10], xmm9, 0x77"); + test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x17, 0b00_001_010, 0x77], "vextractps dword [r10], xmm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x17, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x17, 0b00_001_010, 0x77]); @@ -1511,18 +1512,15 @@ fn test_vex() { test_invalid(&[0xc4, 0b000_00011, 0b1_1111_101, 0x19, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x20, 0b11_001_010, 0x77], "vpinsrb xmm9, xmm8, r10d, 0x77"); - // TODO: byte ptr - test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x20, 0b00_001_010, 0x77], "vpinsrb xmm9, xmm8, [r10], 0x77"); + test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x20, 0b00_001_010, 0x77], "vpinsrb xmm9, xmm8, byte [r10], 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x20, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x21, 0b11_001_010, 0x77], "vinsertps xmm9, xmm8, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x21, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x22, 0b11_001_010, 0x77], "vpinsrd xmm9, xmm8, r10d, 0x77"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x22, 0b00_001_010, 0x77], "vpinsrd xmm9, xmm8, [r10], 0x77"); + test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x22, 0b00_001_010, 0x77], "vpinsrd xmm9, xmm8, dword [r10], 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x22, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b1_0111_001, 0x22, 0b11_001_010, 0x77], "vpinsrq xmm9, xmm8, r10, 0x77"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00011, 0b1_0111_001, 0x22, 0b00_001_010, 0x77], "vpinsrq xmm9, xmm8, [r10], 0x77"); + test_instr(&[0xc4, 0b000_00011, 0b1_0111_001, 0x22, 0b00_001_010, 0x77], "vpinsrq xmm9, xmm8, qword [r10], 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_101, 0x22, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x40, 0b11_001_010, 0x77], "vdpps xmm9, xmm8, xmm10, 0x77"); @@ -1533,8 +1531,7 @@ fn test_vex() { test_avx2(&[0xc4, 0b000_00011, 0b0_0111_101, 0x42, 0b11_001_010, 0x77], "vmpsadbw ymm9, ymm8, ymm10, 0x77"); test_avx2(&[0xc4, 0b000_00011, 0b0_1111_101, 0x46, 0b11_001_010, 0x77], "vperm2i128 ymm9, ymm0, ymm10, 0x77"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00011, 0b0_1111_101, 0x46, 0b00_001_010, 0x77], "vperm2i128 ymm9, ymm0, [r10], 0x77"); + test_avx2(&[0xc4, 0b000_00011, 0b0_1111_101, 0x46, 0b00_001_010, 0x77], "vperm2i128 ymm9, ymm0, ymmword [r10], 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_001, 0x46, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b1_1111_101, 0x46, 0b11_001_010, 0x77]); @@ -1601,8 +1598,7 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x0f, 0b11_001_010], "vtestpd ymm9, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x16, 0b11_001_010], "vpermps ymm9, ymm0, ymm10"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x16, 0b00_001_010], "vpermps ymm9, ymm0, [r10]"); + test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x16, 0b00_001_010], "vpermps ymm9, ymm0, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x16, 0b00_011_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_101, 0x16, 0b00_011_010]); @@ -1611,34 +1607,27 @@ fn test_vex() { test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x17, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x17, 0b11_001_010]); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x18, 0b00_001_010], "vbroadcastss xmm9, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x18, 0b00_001_010], "vbroadcastss ymm9, [r10]"); + test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x18, 0b00_001_010], "vbroadcastss xmm9, dword [r10]"); + test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x18, 0b00_001_010], "vbroadcastss ymm9, dword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_001, 0x18, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x18, 0b00_001_010]); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x19, 0b00_001_010], "vbroadcastsd ymm9, [r10]"); + test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x19, 0b00_001_010], "vbroadcastsd ymm9, qword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x19, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0x19, 0b00_001_010]); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x1a, 0b00_001_010], "vbroadcastf128 ymm9, [r10]"); + test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x1a, 0b00_001_010], "vbroadcastf128 ymm9, xmmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0x1a, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_001, 0x1a, 0b00_001_010]); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x5a, 0b00_001_010], "vbroadcasti128 ymm9, [r10]"); + test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x5a, 0b00_001_010], "vbroadcasti128 ymm9, xmmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_101, 0x5a, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x5a, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_101, 0x5a, 0b00_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x18, 0b11_001_010], "vbroadcastss xmm9, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x18, 0b11_001_010], "vbroadcastss ymm9, xmm10"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x18, 0b00_001_010], "vbroadcastss ymm9, [r10]"); + test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x18, 0b00_001_010], "vbroadcastss ymm9, dword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_001, 0x18, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0x18, 0b11_001_010]); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x19, 0b11_001_010], "vbroadcastsd ymm9, xmm10"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x19, 0b00_001_010], "vbroadcastsd ymm9, [r10]"); + test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x19, 0b00_001_010], "vbroadcastsd ymm9, qword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_101, 0x19, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0x19, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_001, 0x19, 0b11_001_010]); @@ -1681,15 +1670,12 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x29, 0b11_001_010], "vpcmpeqq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x29, 0b11_001_010], "vpcmpeqq ymm9, ymm8, ymm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x2a, 0b11_001_010]); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x2a, 0b00_001_010], "vmovntdqa xmm9, [r10]"); + test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x2a, 0b00_001_010], "vmovntdqa xmm9, xmmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x2a, 0b00_001_010]); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x2a, 0b00_001_010], "vmovntdqa ymm9, [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x2a, 0b00_001_010], "vmovntdqa ymm9, ymmword [r10]"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x2b, 0b11_001_010], "vpackusdw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x2b, 0b11_001_010], "vpackusdw ymm9, ymm8, ymm10"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x2b, 0b00_001_010], "vpackusdw ymm9, ymm8, [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x2b, 0b00_001_010], "vpackusdw ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x30, 0b11_001_010], "vpmovzxbw xmm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x30, 0b11_001_010], "vpmovzxbw ymm9, xmm10"); @@ -1747,96 +1733,62 @@ fn test_vex() { // test_instr(&[0xc4, 0b000_00010, 0b1_0111_001, 0x42, 0b11_001_010], "vphminposuw xmm"); // test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0x41, 0b11_001_010]); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x45, 0b00_001_010], "vpsrlvd xmm9, xmm0, [r10]"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x45, 0b00_001_010], "vpsrlvd ymm9, ymm0, [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x45, 0b00_001_010], "vpsrlvd xmm9, xmm0, xmmword [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x45, 0b00_001_010], "vpsrlvd ymm9, ymm0, ymmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x45, 0b11_001_010], "vpsrlvd xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x45, 0b11_001_010], "vpsrlvd ymm9, ymm0, ymm10"); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x45, 0b00_001_010], "vpsrlvq xmm9, xmm0, [r10]"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x45, 0b00_001_010], "vpsrlvq ymm9, ymm0, [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x45, 0b00_001_010], "vpsrlvq xmm9, xmm0, xmmword [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x45, 0b00_001_010], "vpsrlvq ymm9, ymm0, ymmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x45, 0b11_001_010], "vpsrlvq xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x45, 0b11_001_010], "vpsrlvq ymm9, ymm0, ymm10"); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x46, 0b00_001_010], "vpsravd xmm9, xmm0, [r10]"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x46, 0b00_001_010], "vpsravd ymm9, ymm0, [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x46, 0b00_001_010], "vpsravd xmm9, xmm0, xmmword [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x46, 0b00_001_010], "vpsravd ymm9, ymm0, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_001, 0x46, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_101, 0x46, 0b00_001_010]); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x47, 0b00_001_010], "vpsllvd xmm9, xmm0, [r10]"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x47, 0b00_001_010], "vpsllvd ymm9, ymm0, [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x47, 0b00_001_010], "vpsllvd xmm9, xmm0, xmmword [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x47, 0b00_001_010], "vpsllvd ymm9, ymm0, ymmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x47, 0b11_001_010], "vpsllvd xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x47, 0b11_001_010], "vpsllvd ymm9, ymm0, ymm10"); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x47, 0b00_001_010], "vpsllvq xmm9, xmm0, [r10]"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x47, 0b00_001_010], "vpsllvq ymm9, ymm0, [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x47, 0b00_001_010], "vpsllvq xmm9, xmm0, xmmword [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x47, 0b00_001_010], "vpsllvq ymm9, ymm0, ymmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x47, 0b11_001_010], "vpsllvq xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x47, 0b11_001_010], "vpsllvq ymm9, ymm0, ymm10"); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8c, 0b00_001_010], "vpmaskmovd xmm9, xmm0, [r10]"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x8c, 0b00_001_010], "vpmaskmovd ymm9, ymm0, [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8c, 0b00_001_010], "vpmaskmovd xmm9, xmm0, xmmword [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x8c, 0b00_001_010], "vpmaskmovd ymm9, ymm0, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8c, 0b11_001_010]); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x8c, 0b00_001_010], "vpmaskmovq xmm9, xmm0, [r10]"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x8c, 0b00_001_010], "vpmaskmovq ymm9, ymm0, [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x8c, 0b00_001_010], "vpmaskmovq xmm9, xmm0, xmmword [r10]"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x8c, 0b00_001_010], "vpmaskmovq ymm9, ymm0, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8c, 0b11_001_010]); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8e, 0b00_001_010], "vpmaskmovd [r10], xmm0, xmm9"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x8e, 0b00_001_010], "vpmaskmovd [r10], ymm0, ymm9"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8e, 0b00_001_010], "vpmaskmovd xmmword [r10], xmm0, xmm9"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x8e, 0b00_001_010], "vpmaskmovd ymmword [r10], ymm0, ymm9"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8e, 0b11_001_010]); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x8e, 0b00_001_010], "vpmaskmovq [r10], xmm0, xmm9"); - // TODO: ymmword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x8e, 0b00_001_010], "vpmaskmovq [r10], ymm0, ymm9"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x8e, 0b00_001_010], "vpmaskmovq xmmword [r10], xmm0, xmm9"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x8e, 0b00_001_010], "vpmaskmovq ymmword [r10], ymm0, ymm9"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8e, 0b11_001_010]); - // TODO: dword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x90, 0b00_000_100, 0xa1], "vpgatherdd xmm8, [r9 + xmm12 * 4], xmm0"); - // TODO: qword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x90, 0b00_000_100, 0xa1], "vpgatherdd ymm8, [r9 + ymm12 * 4], ymm0"); - // TODO: dword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x90, 0b00_000_100, 0xa1], "vpgatherdq xmm8, [r9 + xmm12 * 4], xmm0"); - // TODO: qword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x90, 0b00_000_100, 0xa1], "vpgatherdq ymm8, [r9 + ymm12 * 4], ymm0"); - - // TODO: dword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x91, 0b00_000_100, 0xa1], "vpgatherqd xmm8, [r9 + xmm12 * 4], xmm0"); - // TODO: qword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x91, 0b00_000_100, 0xa1], "vpgatherqd ymm8, [r9 + ymm12 * 4], ymm0"); - // TODO: dword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x91, 0b00_000_100, 0xa1], "vpgatherqq xmm8, [r9 + xmm12 * 4], xmm0"); - // TODO: qword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x91, 0b00_000_100, 0xa1], "vpgatherqq ymm8, [r9 + ymm12 * 4], ymm0"); - - // TODO: dword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x92, 0b00_000_100, 0xa1], "vgatherdps xmm8, [r9 + xmm12 * 4], xmm0"); - // TODO: qword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x92, 0b00_000_100, 0xa1], "vgatherdps ymm8, [r9 + ymm12 * 4], ymm0"); - // TODO: dword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x92, 0b00_000_100, 0xa1], "vgatherdpd xmm8, [r9 + xmm12 * 4], xmm0"); - // TODO: qword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x92, 0b00_000_100, 0xa1], "vgatherdpd ymm8, [r9 + ymm12 * 4], ymm0"); - - // TODO: dword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x93, 0b00_000_100, 0xa1], "vgatherqps xmm8, [r9 + xmm12 * 4], xmm0"); - // TODO: qword ptr - test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x93, 0b00_000_100, 0xa1], "vgatherqps ymm8, [r9 + ymm12 * 4], ymm0"); - // TODO: dword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x93, 0b00_000_100, 0xa1], "vgatherqpd xmm8, [r9 + xmm12 * 4], xmm0"); - // TODO: qword ptr - test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x93, 0b00_000_100, 0xa1], "vgatherqpd ymm8, [r9 + ymm12 * 4], ymm0"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x90, 0b00_000_100, 0xa1], "vpgatherdd xmm8, dword [r9 + xmm12 * 4], xmm0"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x90, 0b00_000_100, 0xa1], "vpgatherdd ymm8, dword [r9 + ymm12 * 4], ymm0"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x90, 0b00_000_100, 0xa1], "vpgatherdq xmm8, dword [r9 + xmm12 * 4], xmm0"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x90, 0b00_000_100, 0xa1], "vpgatherdq ymm8, qword [r9 + ymm12 * 4], ymm0"); + + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x91, 0b00_000_100, 0xa1], "vpgatherqd xmm8, dword [r9 + xmm12 * 4], xmm0"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x91, 0b00_000_100, 0xa1], "vpgatherqd xmm8, dword [r9 + ymm12 * 4], xmm0"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x91, 0b00_000_100, 0xa1], "vpgatherqq xmm8, dword [r9 + xmm12 * 4], xmm0"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x91, 0b00_000_100, 0xa1], "vpgatherqq ymm8, qword [r9 + ymm12 * 4], ymm0"); + + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x92, 0b00_000_100, 0xa1], "vgatherdps xmm8, dword [r9 + xmm12 * 4], xmm0"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x92, 0b00_000_100, 0xa1], "vgatherdps ymm8, qword [r9 + ymm12 * 4], ymm0"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x92, 0b00_000_100, 0xa1], "vgatherdpd xmm8, dword [r9 + xmm12 * 4], xmm0"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x92, 0b00_000_100, 0xa1], "vgatherdpd ymm8, qword [r9 + ymm12 * 4], ymm0"); + + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x93, 0b00_000_100, 0xa1], "vgatherqps xmm8, dword [r9 + xmm12 * 4], xmm0"); + test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x93, 0b00_000_100, 0xa1], "vgatherqps ymm8, qword [r9 + ymm12 * 4], ymm0"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x93, 0b00_000_100, 0xa1], "vgatherqpd xmm8, dword [r9 + xmm12 * 4], xmm0"); + test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x93, 0b00_000_100, 0xa1], "vgatherqpd ymm8, qword [r9 + ymm12 * 4], ymm0"); test_instr_vex_aesni(&[0xc4, 0b000_00010, 0b0_1111_001, 0xdb, 0b11_001_010], "vaesimc xmm9, xmm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0xdb, 0b11_001_010]); @@ -1851,112 +1803,74 @@ fn test_vex() { test_instr_vex_aesni(&[0xc4, 0b000_00010, 0b1_0111_101, 0xdf, 0b11_001_010], "vaesdeclast ymm9, ymm8, ymm10"); // prefix 01 - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x10, 0b00_001_010], "vmovsd xmm9, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x10, 0b00_001_010], "vmovsd xmm9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x10, 0b00_001_010], "vmovsd xmm9, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x10, 0b00_001_010], "vmovsd xmm9, qword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_011, 0x10, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_111, 0x10, 0b00_001_010]); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x10, 0b00_001_010], "vmovupd xmm9, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x10, 0b00_001_010], "vmovupd ymm9, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x11, 0b00_001_010], "vmovsd [r10], xmm9"); - // TODO: ... also qword ptr? - test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x11, 0b00_001_010], "vmovsd [r10], xmm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x10, 0b00_001_010], "vmovupd xmm9, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x10, 0b00_001_010], "vmovupd ymm9, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x11, 0b00_001_010], "vmovsd qword [r10], xmm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x11, 0b00_001_010], "vmovsd qword [r10], xmm9"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_011, 0x11, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_111, 0x11, 0b00_001_010]); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x10, 0b00_001_010], "vmovupd xmm9, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x10, 0b00_001_010], "vmovupd ymm9, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x10, 0b00_001_010], "vmovss xmm9, [r10]"); - // TODO: ... also dword ptr? - test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x10, 0b00_001_010], "vmovss xmm9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x10, 0b00_001_010], "vmovupd xmm9, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x10, 0b00_001_010], "vmovupd ymm9, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x10, 0b00_001_010], "vmovss xmm9, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x10, 0b00_001_010], "vmovss xmm9, dword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_010, 0x10, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_110, 0x10, 0b00_001_010]); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x10, 0b00_001_010], "vmovups xmm9, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x10, 0b00_001_010], "vmovups ymm9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x10, 0b00_001_010], "vmovups xmm9, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x10, 0b00_001_010], "vmovups ymm9, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x11, 0b11_001_010], "vmovsd xmm10, xmm8, xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x11, 0b11_001_010], "vmovsd xmm10, xmm8, xmm9"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x11, 0b00_001_010], "vmovss [r10], xmm9"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x11, 0b00_001_010], "vmovss [r10], xmm9"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x11, 0b00_001_010], "vmovups [r10], xmm9"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x11, 0b00_001_010], "vmovups [r10], ymm9"); - - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x12, 0b00_001_010], "vmovddup xmm9, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x12, 0b00_001_010], "vmovddup ymm9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x11, 0b00_001_010], "vmovss dword [r10], xmm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x11, 0b00_001_010], "vmovss dword [r10], xmm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x11, 0b00_001_010], "vmovups xmmword [r10], xmm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x11, 0b00_001_010], "vmovups ymmword [r10], ymm9"); + + test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x12, 0b00_001_010], "vmovddup xmm9, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x12, 0b00_001_010], "vmovddup ymm9, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_011, 0x12, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_111, 0x12, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x12, 0b11_001_010], "vmovhlps xmm9, xmm8, xmm10"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x12, 0b00_001_010], "vmovlps xmm9, xmm8, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x12, 0b00_001_010], "vmovlps xmm9, xmm8, dword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_100, 0x12, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_111, 0x12, 0b11_001_010]); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x12, 0b00_001_010], "vmovsldup xmm9, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x12, 0b00_001_010], "vmovsldup ymm9, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x12, 0b00_001_010], "vmovsldup xmm9, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x12, 0b00_001_010], "vmovsldup ymm9, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x12, 0b00_001_010], "vmovlpd xmm9, xmm8, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x12, 0b00_001_010], "vmovsldup xmm9, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x12, 0b00_001_010], "vmovsldup ymm9, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x12, 0b00_001_010], "vmovsldup xmm9, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x12, 0b00_001_010], "vmovsldup ymm9, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x12, 0b00_001_010], "vmovlpd xmm9, xmm8, qword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_101, 0x12, 0b00_001_010]); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x13, 0b00_001_010], "vmovlpd [r10], xmm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x13, 0b00_001_010], "vmovlpd qword [r10], xmm9"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_001, 0x13, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_101, 0x13, 0b00_001_010]); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_000, 0x14, 0b11_001_010], "vunpcklps xmm9, xmm8, xmm10"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_100, 0x14, 0b11_001_010], "vunpcklps ymm9, ymm8, ymm10"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x14, 0b11_001_010], "vunpcklpd xmm9, xmm8, xmm10"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_101, 0x14, 0b11_001_010], "vunpcklpd ymm9, ymm8, ymm10"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_000, 0x15, 0b11_001_010], "vunpckhps xmm9, xmm8, xmm10"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_100, 0x15, 0b11_001_010], "vunpckhps ymm9, ymm8, ymm10"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x15, 0b11_001_010], "vunpckhpd xmm9, xmm8, xmm10"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_101, 0x15, 0b11_001_010], "vunpckhpd ymm9, ymm8, ymm10"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_000, 0x14, 0b00_001_010], "vunpcklps xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_100, 0x14, 0b00_001_010], "vunpcklps ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x14, 0b00_001_010], "vunpcklpd xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_101, 0x14, 0b00_001_010], "vunpcklpd ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_000, 0x15, 0b00_001_010], "vunpckhps xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_100, 0x15, 0b00_001_010], "vunpckhps ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x15, 0b00_001_010], "vunpckhpd xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_101, 0x15, 0b00_001_010], "vunpckhpd ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x16, 0b11_001_010], "vmovshdup xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x16, 0b11_001_010], "vmovshdup ymm9, ymm10"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_010, 0x16, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_110, 0x16, 0b11_001_010]); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x16, 0b00_001_010], "vmovhps xmm9, xmm8, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x16, 0b00_001_010], "vmovhps xmm9, xmm8, qword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_100, 0x16, 0b00_001_010]); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x16, 0b00_001_010], "vmovhpd xmm9, xmm8, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x16, 0b00_001_010], "vmovhpd xmm9, xmm8, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x16, 0b00_001_010], "vmovhpd xmm9, xmm8, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x16, 0b00_001_010], "vmovhpd xmm9, xmm8, qword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_001, 0x16, 0b11_001_010]); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x17, 0b00_001_010], "vmovhps [r10], xmm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x17, 0b00_001_010], "vmovhps qword [r10], xmm9"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_100, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_000, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_100, 0x17, 0b00_001_010]); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x17, 0b00_001_010], "vmovhpd [r10], xmm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x17, 0b00_001_010], "vmovhpd qword [r10], xmm9"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_001, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0x17, 0b00_001_010]); @@ -1970,81 +1884,62 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x29, 0b11_001_010], "vmovapd ymm10, ymm9"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x2a, 0b11_001_010], "vcvtsi2ss xmm9, xmm0, r10d"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x2a, 0b00_001_010], "vcvtsi2ss xmm9, xmm0, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x2a, 0b00_001_010], "vcvtsi2ss xmm9, xmm0, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x2a, 0b11_001_010], "vcvtsi2ss xmm9, xmm0, r10"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x2a, 0b00_001_010], "vcvtsi2ss xmm9, xmm0, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x2a, 0b00_001_010], "vcvtsi2ss xmm9, xmm0, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x2a, 0b11_001_010], "vcvtsi2ss xmm9, xmm0, r10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2a, 0b11_001_010], "vcvtsi2sd xmm9, xmm0, r10d"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2a, 0b11_001_010], "vcvtsi2sd xmm9, xmm0, r10d"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x2a, 0b11_001_010], "vcvtsi2sd xmm9, xmm0, r10"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2a, 0b00_001_010], "vcvtsi2sd xmm9, xmm0, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x2a, 0b00_001_010], "vcvtsi2sd xmm9, xmm0, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2a, 0b00_001_010], "vcvtsi2sd xmm9, xmm0, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x2a, 0b00_001_010], "vcvtsi2sd xmm9, xmm0, qword [r10]"); test_instr(&[0xc5, 0b0_1111_011, 0x2a, 0b11_001_010], "vcvtsi2sd xmm9, xmm0, edx"); test_instr(&[0xc5, 0b0_1111_111, 0x2a, 0b11_001_010], "vcvtsi2sd xmm9, xmm0, edx"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0x2b, 0b00_001_010], "vmovntps [r10], xmm9"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x2b, 0b00_001_010], "vmovntps [r10], ymm9"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0x2b, 0b00_001_010], "vmovntps xmmword [r10], xmm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x2b, 0b00_001_010], "vmovntps ymmword [r10], ymm9"); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_000, 0x2b, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_100, 0x2b, 0b11_001_010]); - test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2b, 0b00_001_010], "vmovntpd [r10], xmm9"); - test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x2b, 0b00_001_010], "vmovntpd [r10], ymm9"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2b, 0b00_001_010], "vmovntpd xmmword [r10], xmm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x2b, 0b00_001_010], "vmovntpd ymmword [r10], ymm9"); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2b, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0x2b, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x2c, 0b11_001_010], "vcvttss2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x2c, 0b11_001_010], "vcvttss2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x2c, 0b11_001_010], "vcvttss2si r9, xmm10"); test_instr(&[0xc5, 0b0_1111_010, 0x2c, 0b11_001_010], "vcvttss2si r9d, xmm2"); - // TODO: dword ptr - test_instr(&[0xc5, 0b0_1111_010, 0x2c, 0b00_001_010], "vcvttss2si r9d, [rdx]"); + test_instr(&[0xc5, 0b0_1111_010, 0x2c, 0b00_001_010], "vcvttss2si r9d, dword [rdx]"); test_instr(&[0xc5, 0b0_1111_110, 0x2c, 0b11_001_010], "vcvttss2si r9d, xmm2"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2c, 0b11_001_010], "vcvttsd2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2c, 0b11_001_010], "vcvttsd2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x2c, 0b11_001_010], "vcvttsd2si r9, xmm10"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si r9, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si r9d, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si r9, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si r9d, dword [r10]"); test_instr(&[0xc5, 0b0_1111_011, 0x2c, 0b11_001_010], "vcvttsd2si r9d, xmm2"); test_instr(&[0xc5, 0b0_1111_111, 0x2c, 0b11_001_010], "vcvttsd2si r9d, xmm2"); - // TODO: qword ptr - test_instr(&[0xc5, 0b0_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si r9d, [rdx]"); + test_instr(&[0xc5, 0b0_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si r9d, dword [rdx]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x2d, 0b11_001_010], "vcvtss2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x2d, 0b11_001_010], "vcvtss2si r9d, xmm10"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x2d, 0b00_001_010], "vcvtss2si r9d, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x2d, 0b00_001_010], "vcvtss2si r9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x2d, 0b00_001_010], "vcvtss2si r9d, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x2d, 0b00_001_010], "vcvtss2si r9, dword [r10]"); test_instr(&[0xc5, 0b0_1111_010, 0x2d, 0b11_001_010], "vcvtss2si r9d, xmm2"); test_instr(&[0xc5, 0b0_1111_110, 0x2d, 0b11_001_010], "vcvtss2si r9d, xmm2"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2d, 0b11_001_010], "vcvtsd2si r9d, xmm10"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2d, 0b00_001_010], "vcvtsd2si r9d, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2d, 0b00_001_010], "vcvtsd2si r9d, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2d, 0b11_001_010], "vcvtsd2si r9d, xmm10"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2d, 0b00_001_010], "vcvtsd2si r9d, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2d, 0b00_001_010], "vcvtsd2si r9d, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x2d, 0b11_001_010], "vcvtsd2si r9, xmm10"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x2d, 0b00_001_010], "vcvtsd2si r9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x2d, 0b00_001_010], "vcvtsd2si r9, qword [r10]"); test_instr(&[0xc5, 0b0_1111_011, 0x2d, 0b11_001_010], "vcvtsd2si r9d, xmm2"); test_instr(&[0xc5, 0b0_1111_111, 0x2d, 0b11_001_010], "vcvtsd2si r9d, xmm2"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2e, 0b00_001_010], "vucomisd xmm9, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x2e, 0b00_001_010], "vucomisd xmm9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2e, 0b00_001_010], "vucomisd xmm9, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x2e, 0b00_001_010], "vucomisd xmm9, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2e, 0b11_001_010], "vucomisd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x2e, 0b11_001_010], "vucomisd xmm9, xmm10"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2f, 0b00_001_010], "vcomisd xmm9, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x2f, 0b00_001_010], "vcomisd xmm9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2f, 0b00_001_010], "vcomisd xmm9, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x2f, 0b00_001_010], "vcomisd xmm9, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2f, 0b11_001_010], "vcomisd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x2f, 0b11_001_010], "vcomisd xmm9, xmm10"); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_001, 0x2e, 0b00_001_010]); @@ -2057,11 +1952,9 @@ fn test_vex() { test_invalid(&[0xc4, 0b000_00001, 0b0_0111_101, 0x2f, 0b11_001_010]); test_instr(&[0xc5, 0b0_1111_000, 0x2e, 0b11_001_010], "vucomiss xmm9, xmm2"); - // TODO: dword ptr - test_instr(&[0xc5, 0b0_1111_100, 0x2e, 0b00_001_010], "vucomiss xmm9, [rdx]"); + test_instr(&[0xc5, 0b0_1111_100, 0x2e, 0b00_001_010], "vucomiss xmm9, dword [rdx]"); test_instr(&[0xc5, 0b0_1111_000, 0x2f, 0b11_001_010], "vcomiss xmm9, xmm2"); - // TODO: dword ptr - test_instr(&[0xc5, 0b0_1111_100, 0x2f, 0b00_001_010], "vcomiss xmm9, [rdx]"); + test_instr(&[0xc5, 0b0_1111_100, 0x2f, 0b00_001_010], "vcomiss xmm9, dword [rdx]"); test_invalid(&[0xc5, 0b0_1111_111, 0x2f, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x50, 0b11_001_010], "vmovmskps r9d, xmm10"); @@ -2078,24 +1971,16 @@ fn test_vex() { test_invalid(&[0xc4, 0b000_00001, 0b1_0111_001, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_101, 0x50, 0b00_001_010]); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x51, 0b00_001_010], "vsqrtpd xmm9, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x51, 0b00_001_010], "vsqrtpd ymm9, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_011, 0x51, 0b00_001_010], "vsqrtsd xmm9, xmm8, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_111, 0x51, 0b00_001_010], "vsqrtsd xmm9, xmm8, [r10]"); - - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x51, 0b11_001_010], "vsqrtps xmm9, xmm10"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x51, 0b00_001_010], "vsqrtpd xmm9, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x51, 0b00_001_010], "vsqrtpd ymm9, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_011, 0x51, 0b00_001_010], "vsqrtsd xmm9, xmm8, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_111, 0x51, 0b00_001_010], "vsqrtsd xmm9, xmm8, qword [r10]"); + + test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x51, 0b00_001_010], "vsqrtps xmm9, xmmword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_000, 0x51, 0b11_001_010]); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x51, 0b11_001_010], "vsqrtps ymm9, ymm10"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x51, 0b00_001_010], "vsqrtss xmm9, xmm0, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x51, 0b00_001_010], "vsqrtss xmm9, xmm0, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x51, 0b00_001_010], "vsqrtps ymm9, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x51, 0b00_001_010], "vsqrtss xmm9, xmm0, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x51, 0b00_001_010], "vsqrtss xmm9, xmm0, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x52, 0b11_001_010], "vrsqrtps xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x52, 0b11_001_010], "vrsqrtps ymm9, ymm10"); @@ -2111,22 +1996,14 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x55, 0b11_001_010], "vandnps xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x55, 0b11_001_010], "vandnps ymm9, ymm8, ymm10"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x54, 0b00_001_010], "vandpd xmm9, xmm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x54, 0b00_001_010], "vandpd ymm9, ymm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x55, 0b00_001_010], "vandnpd xmm9, xmm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x55, 0b00_001_010], "vandnpd ymm9, ymm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x56, 0b00_001_010], "vorpd xmm9, xmm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x56, 0b00_001_010], "vorpd ymm9, ymm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x56, 0b00_001_010], "vorps xmm9, xmm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x56, 0b00_001_010], "vorps ymm9, ymm8, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x54, 0b00_001_010], "vandpd xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x54, 0b00_001_010], "vandpd ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x55, 0b00_001_010], "vandnpd xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x55, 0b00_001_010], "vandnpd ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x56, 0b00_001_010], "vorpd xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x56, 0b00_001_010], "vorpd ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x56, 0b00_001_010], "vorps xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x56, 0b00_001_010], "vorps ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x57, 0b11_001_010], "vxorps xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x57, 0b11_001_010], "vxorps ymm9, ymm8, ymm10"); @@ -2136,42 +2013,26 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x58, 0b11_001_010], "vaddps ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x58, 0b11_001_010], "vaddss xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x58, 0b11_001_010], "vaddss xmm9, xmm8, xmm10"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x58, 0b00_001_010], "vaddss xmm9, xmm8, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x58, 0b00_001_010], "vaddss xmm9, xmm8, [r10]"); - - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x58, 0b00_001_010], "vaddpd xmm9, xmm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x58, 0b00_001_010], "vaddpd ymm9, ymm8, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x58, 0b00_001_010], "vaddsd xmm9, xmm8, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x58, 0b00_001_010], "vaddsd xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x59, 0b00_001_010], "vmulps xmm9, xmm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x59, 0b00_001_010], "vmulps ymm9, ymm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x59, 0b00_001_010], "vmulpd xmm9, xmm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x59, 0b00_001_010], "vmulpd ymm9, ymm8, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x59, 0b00_001_010], "vmulss xmm9, xmm8, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x59, 0b00_001_010], "vmulss xmm9, xmm8, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x59, 0b00_001_010], "vmulsd xmm9, xmm8, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x59, 0b00_001_010], "vmulsd xmm9, xmm8, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x58, 0b00_001_010], "vaddss xmm9, xmm8, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x58, 0b00_001_010], "vaddss xmm9, xmm8, dword [r10]"); + + test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x58, 0b00_001_010], "vaddpd xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x58, 0b00_001_010], "vaddpd ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x58, 0b00_001_010], "vaddsd xmm9, xmm8, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x58, 0b00_001_010], "vaddsd xmm9, xmm8, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x59, 0b00_001_010], "vmulps xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x59, 0b00_001_010], "vmulps ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x59, 0b00_001_010], "vmulpd xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x59, 0b00_001_010], "vmulpd ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x59, 0b00_001_010], "vmulss xmm9, xmm8, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x59, 0b00_001_010], "vmulss xmm9, xmm8, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x59, 0b00_001_010], "vmulsd xmm9, xmm8, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x59, 0b00_001_010], "vmulsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x5a, 0b11_001_010], "vcvtps2pd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x5a, 0b11_001_010], "vcvtps2pd ymm9, xmm10"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x5a, 0b00_001_010], "vcvtps2pd xmm9, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x5a, 0b00_001_010], "vcvtps2pd ymm9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x5a, 0b00_001_010], "vcvtps2pd xmm9, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x5a, 0b00_001_010], "vcvtps2pd ymm9, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x5a, 0b11_001_010], "vcvtpd2ps xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x5a, 0b11_001_010], "vcvtpd2ps xmm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x5a, 0b11_001_010], "vcvtsd2ss xmm9, xmm0, xmm10"); @@ -2184,80 +2045,45 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x5b, 0b11_001_010], "vcvttps2dq xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x5b, 0b11_001_010], "vcvttps2dq ymm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x5b, 0b11_001_010], "vcvtdq2ps xmm9, xmm10"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x5b, 0b00_001_010], "vcvtdq2ps xmm9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x5b, 0b00_001_010], "vcvtdq2ps xmm9, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x5b, 0b11_001_010], "vcvtdq2ps ymm9, ymm10"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x5b, 0b00_001_010], "vcvtdq2ps ymm9, [r10]"); - - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0x5c, 0b00_001_010], "vsubps xmm9, xmm0, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_100, 0x5c, 0b00_001_010], "vsubps ymm9, ymm0, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_010, 0x5c, 0b00_001_010], "vsubss xmm9, xmm8, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_110, 0x5c, 0b00_001_010], "vsubss xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x5c, 0b00_001_010], "vsubpd xmm9, xmm0, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x5c, 0b00_001_010], "vsubpd ymm9, ymm0, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_011, 0x5c, 0b00_001_010], "vsubsd xmm9, xmm8, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_0111_111, 0x5c, 0b00_001_010], "vsubsd xmm9, xmm8, [r10]"); - - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5d, 0b00_001_010], "vminps xmm9, xmm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x5d, 0b00_001_010], "vminps ymm9, ymm8, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x5d, 0b00_001_010], "vminss xmm9, xmm8, [r10]"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x5d, 0b00_001_010], "vminss xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x5d, 0b00_001_010], "vminpd xmm9, xmm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x5d, 0b00_001_010], "vminpd ymm9, ymm8, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x5d, 0b00_001_010], "vminsd xmm9, xmm8, [r10]"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x5d, 0b00_001_010], "vminsd xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5e, 0b00_001_010], "vdivps xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5e, 0b00_001_010], "vdivps xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x5e, 0b00_001_010], "vdivpd xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x5e, 0b00_001_010], "vdivss xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x5e, 0b00_001_010], "vdivsd xmm9, xmm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x5e, 0b00_001_010], "vdivps ymm9, ymm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x5e, 0b00_001_010], "vdivpd ymm9, ymm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x5e, 0b00_001_010], "vdivss xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x5e, 0b00_001_010], "vdivsd xmm9, xmm8, [r10]"); - - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5f, 0b00_001_010], "vmaxps xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x5f, 0b00_001_010], "vmaxpd xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x5f, 0b00_001_010], "vmaxss xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x5f, 0b00_001_010], "vmaxsd xmm9, xmm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x5f, 0b00_001_010], "vmaxps ymm9, ymm8, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x5f, 0b00_001_010], "vmaxpd ymm9, ymm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x5f, 0b00_001_010], "vmaxss xmm9, xmm8, [r10]"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x5f, 0b00_001_010], "vmaxsd xmm9, xmm8, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x5b, 0b00_001_010], "vcvtdq2ps ymm9, ymmword [r10]"); + + test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0x5c, 0b00_001_010], "vsubps xmm9, xmm0, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_100, 0x5c, 0b00_001_010], "vsubps ymm9, ymm0, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_010, 0x5c, 0b00_001_010], "vsubss xmm9, xmm8, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_110, 0x5c, 0b00_001_010], "vsubss xmm9, xmm8, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x5c, 0b00_001_010], "vsubpd xmm9, xmm0, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x5c, 0b00_001_010], "vsubpd ymm9, ymm0, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_011, 0x5c, 0b00_001_010], "vsubsd xmm9, xmm8, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b0_0111_111, 0x5c, 0b00_001_010], "vsubsd xmm9, xmm8, qword [r10]"); + + test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5d, 0b00_001_010], "vminps xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x5d, 0b00_001_010], "vminps ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x5d, 0b00_001_010], "vminss xmm9, xmm8, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x5d, 0b00_001_010], "vminss xmm9, xmm8, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x5d, 0b00_001_010], "vminpd xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x5d, 0b00_001_010], "vminpd ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x5d, 0b00_001_010], "vminsd xmm9, xmm8, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x5d, 0b00_001_010], "vminsd xmm9, xmm8, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5e, 0b00_001_010], "vdivps xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5e, 0b00_001_010], "vdivps xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x5e, 0b00_001_010], "vdivpd xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x5e, 0b00_001_010], "vdivss xmm9, xmm8, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x5e, 0b00_001_010], "vdivsd xmm9, xmm8, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x5e, 0b00_001_010], "vdivps ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x5e, 0b00_001_010], "vdivpd ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x5e, 0b00_001_010], "vdivss xmm9, xmm8, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x5e, 0b00_001_010], "vdivsd xmm9, xmm8, qword [r10]"); + + test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5f, 0b00_001_010], "vmaxps xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x5f, 0b00_001_010], "vmaxpd xmm9, xmm8, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x5f, 0b00_001_010], "vmaxss xmm9, xmm8, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x5f, 0b00_001_010], "vmaxsd xmm9, xmm8, qword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x5f, 0b00_001_010], "vmaxps ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x5f, 0b00_001_010], "vmaxpd ymm9, ymm8, ymmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x5f, 0b00_001_010], "vmaxss xmm9, xmm8, dword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x5f, 0b00_001_010], "vmaxsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x60, 0b11_001_010], "vpunpcklbw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x60, 0b11_001_010], "vpunpcklbw ymm9, ymm8, ymm10"); @@ -2293,8 +2119,7 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x6d, 0b11_001_010], "vpunpckhqdq xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x6d, 0b11_001_010], "vpunpckhqdq ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x6e, 0b11_001_010], "vmovq xmm9, r10"); - // TODO: qword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x6e, 0b00_001_010], "vmovq xmm9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x6e, 0b00_001_010], "vmovq xmm9, qword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0x6e, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x6f, 0b11_001_010], "vmovdqa xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x6f, 0b11_001_010], "vmovdqa ymm9, ymm10"); @@ -2371,12 +2196,10 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x7f, 0b11_001_010], "vmovdqu xmm10, xmm9"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x7f, 0b11_001_010], "vmovdqu ymm10, ymm9"); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b00_010_001], "vldmxcsr [r9]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b00_010_001], "vldmxcsr dword [r9]"); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_100, 0xae, 0b00_010_001]); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b11_010_001]); - // TODO: dword ptr - test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b00_011_001], "vstmxcsr [r9]"); + test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b00_011_001], "vstmxcsr dword [r9]"); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_100, 0xae, 0b00_011_001]); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b11_011_001]); @@ -2405,16 +2228,13 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xd1, 0b11_001_010], "vpsrlw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd1, 0b11_001_010], "vpsrlw ymm9, ymm8, xmm10"); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd1, 0b00_001_010], "vpsrlw ymm9, ymm8, [r10]"); + test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd1, 0b00_001_010], "vpsrlw ymm9, ymm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xd2, 0b11_001_010], "vpsrld xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd2, 0b11_001_010], "vpsrld ymm9, ymm8, xmm10"); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd2, 0b00_001_010], "vpsrld ymm9, ymm8, [r10]"); + test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd2, 0b00_001_010], "vpsrld ymm9, ymm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xd3, 0b11_001_010], "vpsrlq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd3, 0b11_001_010], "vpsrlq ymm9, ymm8, xmm10"); - // TODO: xmmword ptr - test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd3, 0b00_001_010], "vpsrlq ymm9, ymm8, [r10]"); + test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd3, 0b00_001_010], "vpsrlq ymm9, ymm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xd4, 0b11_001_010], "vpaddq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd4, 0b11_001_010], "vpaddq ymm9, ymm8, ymm10"); @@ -2464,8 +2284,8 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0xe6, 0b11_001_010], "vcvtpd2dq xmm9, ymm10"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0xe7, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0xe7, 0b11_001_010]); - test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0xe7, 0b00_001_010], "vmovntdq [r10], xmm9"); - test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0xe7, 0b00_001_010], "vmovntdq [r10], ymm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0xe7, 0b00_001_010], "vmovntdq xmmword [r10], xmm9"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0xe7, 0b00_001_010], "vmovntdq ymmword [r10], ymm9"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xe8, 0b11_001_010], "vpsubsb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xe8, 0b11_001_010], "vpsubsb ymm9, ymm8, ymm10"); @@ -2485,10 +2305,8 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0xef, 0b11_001_010], "vpxor xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0xef, 0b11_001_010], "vpxor ymm9, ymm8, ymm10"); - // TODO: xmmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0xf0, 0b00_001_010], "vlddqu xmm9, [r10]"); - // TODO: ymmword ptr - test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0xf0, 0b00_001_010], "vlddqu ymm9, [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0xf0, 0b00_001_010], "vlddqu xmm9, xmmword [r10]"); + test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0xf0, 0b00_001_010], "vlddqu ymm9, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_011, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_011, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_111, 0xf0, 0b11_001_010]); @@ -2526,98 +2344,98 @@ fn test_vex() { test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xfe, 0b11_001_010], "vpaddd xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xfe, 0b11_001_010], "vpaddd ymm9, ymm8, ymm10"); - test_instr(&[0xc5, 0xf8, 0x10, 0x00], "vmovups xmm0, [rax]"); - test_instr(&[0xc5, 0xf8, 0x10, 0x01], "vmovups xmm0, [rcx]"); - test_instr(&[0xc5, 0x78, 0x10, 0x0f], "vmovups xmm9, [rdi]"); + test_instr(&[0xc5, 0xf8, 0x10, 0x00], "vmovups xmm0, xmmword [rax]"); + test_instr(&[0xc5, 0xf8, 0x10, 0x01], "vmovups xmm0, xmmword [rcx]"); + test_instr(&[0xc5, 0x78, 0x10, 0x0f], "vmovups xmm9, xmmword [rdi]"); test_instr(&[0xc5, 0xf8, 0x10, 0xcf], "vmovups xmm1, xmm7"); - test_instr(&[0xc5, 0xf9, 0x10, 0x0f], "vmovupd xmm1, [rdi]"); - test_instr(&[0xc5, 0xfa, 0x7e, 0x10], "vmovq xmm2, [rax]"); - test_instr(&[0xc5, 0xfc, 0x10, 0x0f], "vmovups ymm1, [rdi]"); - test_instr(&[0xc5, 0xfd, 0x10, 0x0f], "vmovupd ymm1, [rdi]"); - test_instr(&[0xc5, 0xfe, 0x10, 0x0f], "vmovss xmm1, [rdi]"); + test_instr(&[0xc5, 0xf9, 0x10, 0x0f], "vmovupd xmm1, xmmword [rdi]"); + test_instr(&[0xc5, 0xfa, 0x7e, 0x10], "vmovq xmm2, qword [rax]"); + test_instr(&[0xc5, 0xfc, 0x10, 0x0f], "vmovups ymm1, ymmword [rdi]"); + test_instr(&[0xc5, 0xfd, 0x10, 0x0f], "vmovupd ymm1, ymmword [rdi]"); + test_instr(&[0xc5, 0xfe, 0x10, 0x0f], "vmovss xmm1, dword [rdi]"); test_instr(&[0xc5, 0xff, 0x10, 0xcf], "vmovsd xmm1, xmm0, xmm7"); - test_instr(&[0xc5, 0xff, 0x10, 0x01], "vmovsd xmm0, [rcx]"); + test_instr(&[0xc5, 0xff, 0x10, 0x01], "vmovsd xmm0, qword [rcx]"); test_instr(&[0xc5, 0xf9, 0x6e, 0xc6], "vmovd xmm0, esi"); - test_instr(&[0xc5, 0xf9, 0x6e, 0x13], "vmovd xmm2, [rbx]"); + test_instr(&[0xc5, 0xf9, 0x6e, 0x13], "vmovd xmm2, dword [rbx]"); test_instr(&[0xc5, 0xf9, 0x7e, 0xc6], "vmovd esi, xmm0"); - test_instr(&[0xc5, 0xf9, 0x7e, 0x13], "vmovd [rbx], xmm2"); + test_instr(&[0xc5, 0xf9, 0x7e, 0x13], "vmovd dword [rbx], xmm2"); test_instr_invalid(&[0x4f, 0xc5, 0xf8, 0x10, 0x00]); test_instr_invalid(&[0xf0, 0xc5, 0xf8, 0x10, 0x00]); - test_instr(&[0xc4, 0x02, 0x71, 0x00, 0x0f], "vpshufb xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x00, 0x0f], "vpshufb ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x00, 0x0f], "vpshufb xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x00, 0x0f], "vpshufb ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x00, 0xcd], "vpshufb xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x00, 0xcd], "vpshufb ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x01, 0x0f], "vphaddw xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x01, 0x0f], "vphaddw ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x01, 0x0f], "vphaddw xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x01, 0x0f], "vphaddw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x01, 0xcd], "vphaddw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x01, 0xcd], "vphaddw ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x02, 0x0f], "vphaddd xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x02, 0x0f], "vphaddd ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x02, 0x0f], "vphaddd xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x02, 0x0f], "vphaddd ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x02, 0xcd], "vphaddd xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x02, 0xcd], "vphaddd ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x03, 0x0f], "vphaddsw xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x03, 0x0f], "vphaddsw ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x03, 0x0f], "vphaddsw xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x03, 0x0f], "vphaddsw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x03, 0xcd], "vphaddsw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x03, 0xcd], "vphaddsw ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x04, 0x0f], "vpmaddubsw xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x04, 0x0f], "vpmaddubsw ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x04, 0x0f], "vpmaddubsw xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x04, 0x0f], "vpmaddubsw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x04, 0xcd], "vpmaddubsw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x04, 0xcd], "vpmaddubsw ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x05, 0x0f], "vphsubw xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x05, 0x0f], "vphsubw ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x05, 0x0f], "vphsubw xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x05, 0x0f], "vphsubw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x05, 0xcd], "vphsubw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x05, 0xcd], "vphsubw ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x06, 0x0f], "vphsubd xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x06, 0x0f], "vphsubd ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x06, 0x0f], "vphsubd xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x06, 0x0f], "vphsubd ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x06, 0xcd], "vphsubd xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x06, 0xcd], "vphsubd ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x07, 0x0f], "vphsubsw xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x07, 0x0f], "vphsubsw ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x07, 0x0f], "vphsubsw xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x07, 0x0f], "vphsubsw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x07, 0xcd], "vphsubsw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x07, 0xcd], "vphsubsw ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x08, 0x0f], "vpsignb xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x08, 0x0f], "vpsignb ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x08, 0x0f], "vpsignb xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x08, 0x0f], "vpsignb ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x08, 0xcd], "vpsignb xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x08, 0xcd], "vpsignb ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x09, 0x0f], "vpsignw xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x09, 0x0f], "vpsignw ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x09, 0x0f], "vpsignw xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x09, 0x0f], "vpsignw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x09, 0xcd], "vpsignw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x09, 0xcd], "vpsignw ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x0a, 0x0f], "vpsignd xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x0a, 0x0f], "vpsignd ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x0a, 0x0f], "vpsignd xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x0a, 0x0f], "vpsignd ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x0a, 0xcd], "vpsignd xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x0a, 0xcd], "vpsignd ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x0b, 0x0f], "vpmulhrsw xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x0b, 0x0f], "vpmulhrsw ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x0b, 0x0f], "vpmulhrsw xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x0b, 0x0f], "vpmulhrsw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x0b, 0xcd], "vpmulhrsw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x0b, 0xcd], "vpmulhrsw ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x0c, 0x0f], "vpermilps xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x0c, 0x0f], "vpermilps ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x0c, 0x0f], "vpermilps xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x0c, 0x0f], "vpermilps ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x0c, 0xcd], "vpermilps xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x0c, 0xcd], "vpermilps ymm9, ymm1, ymm13"); - test_instr(&[0xc4, 0x02, 0x71, 0x0d, 0x0f], "vpermilpd xmm9, xmm1, [r15]"); - test_instr(&[0xc4, 0x02, 0x75, 0x0d, 0x0f], "vpermilpd ymm9, ymm1, [r15]"); + test_instr(&[0xc4, 0x02, 0x71, 0x0d, 0x0f], "vpermilpd xmm9, xmm1, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x75, 0x0d, 0x0f], "vpermilpd ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x0d, 0xcd], "vpermilpd xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x0d, 0xcd], "vpermilpd ymm9, ymm1, ymm13"); test_instr_invalid(&[0xc4, 0x02, 0x71, 0x0e, 0x00]); - test_instr(&[0xc4, 0x02, 0x79, 0x0e, 0x0f], "vtestps xmm9, [r15]"); - test_instr(&[0xc4, 0x02, 0x7d, 0x0e, 0x0f], "vtestps ymm9, [r15]"); + test_instr(&[0xc4, 0x02, 0x79, 0x0e, 0x0f], "vtestps xmm9, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x7d, 0x0e, 0x0f], "vtestps ymm9, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x79, 0x0e, 0xcd], "vtestps xmm9, xmm13"); test_instr(&[0xc4, 0x02, 0x7d, 0x0e, 0xcd], "vtestps ymm9, ymm13"); test_instr_invalid(&[0xc4, 0x02, 0x71, 0x0f, 0x00]); - test_instr(&[0xc4, 0x02, 0x79, 0x0f, 0x0f], "vtestpd xmm9, [r15]"); - test_instr(&[0xc4, 0x02, 0x7d, 0x0f, 0x0f], "vtestpd ymm9, [r15]"); + test_instr(&[0xc4, 0x02, 0x79, 0x0f, 0x0f], "vtestpd xmm9, xmmword [r15]"); + test_instr(&[0xc4, 0x02, 0x7d, 0x0f, 0x0f], "vtestpd ymm9, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x79, 0x0f, 0xcd], "vtestpd xmm9, xmm13"); test_instr(&[0xc4, 0x02, 0x7d, 0x0f, 0xcd], "vtestpd ymm9, ymm13"); - test_instr(&[0xc4, 0xe2, 0x65, 0x90, 0x04, 0x51], "vpgatherdd ymm0, [rcx + ymm2 * 2], ymm3"); - test_instr(&[0xc4, 0xe2, 0xe5, 0x90, 0x04, 0x51], "vpgatherdq ymm0, [rcx + ymm2 * 2], ymm3"); - test_instr(&[0xc4, 0xe2, 0x65, 0x91, 0x04, 0x51], "vpgatherqd ymm0, [rcx + ymm2 * 2], ymm3"); - test_instr(&[0xc4, 0xe2, 0xe5, 0x91, 0x04, 0x51], "vpgatherqq ymm0, [rcx + ymm2 * 2], ymm3"); + test_instr(&[0xc4, 0xe2, 0x65, 0x90, 0x04, 0x51], "vpgatherdd ymm0, dword [rcx + ymm2 * 2], ymm3"); + test_instr(&[0xc4, 0xe2, 0xe5, 0x90, 0x04, 0x51], "vpgatherdq ymm0, qword [rcx + ymm2 * 2], ymm3"); + test_instr(&[0xc4, 0xe2, 0x65, 0x91, 0x04, 0x51], "vpgatherqd xmm0, dword [rcx + ymm2 * 2], xmm3"); + test_instr(&[0xc4, 0xe2, 0xe5, 0x91, 0x04, 0x51], "vpgatherqq ymm0, qword [rcx + ymm2 * 2], ymm3"); test_instr(&[0xc4, 0x02, 0x09, 0x9d, 0xcd], "vfnmadd132ss xmm9, xmm14, xmm13"); test_instr(&[0xc4, 0x02, 0x89, 0x9d, 0xcd], "vfnmadd132sd xmm9, xmm14, xmm13"); // ... test_instr(&[0xc4, 0xe3, 0x79, 0x14, 0xd0, 0x0a], "vpextrb eax, xmm2, 0xa"); - test_instr(&[0xc4, 0xe3, 0x79, 0x14, 0x10, 0x0a], "vpextrb [rax], xmm2, 0xa"); + test_instr(&[0xc4, 0xe3, 0x79, 0x14, 0x10, 0x0a], "vpextrb byte [rax], xmm2, 0xa"); test_instr_invalid(&[0xc4, 0xe3, 0xf9, 0x14, 0x00, 0xd0]); test_instr_invalid(&[0xc4, 0xe3, 0xf9, 0x14, 0x00, 0x0a]); test_instr(&[0xc5, 0xed, 0x71, 0xd0, 0x04], "vpsrlw ymm2, ymm0, 0x4"); @@ -2626,40 +2444,40 @@ fn test_vex() { test_instr(&[0xc5, 0xfd, 0xea, 0xd1], "vpminsw ymm2, ymm0, ymm1"); test_instr(&[0xc5, 0xfd, 0xee, 0xd9], "vpmaxsw ymm3, ymm0, ymm1"); test_instr(&[0xc4, 0xe3, 0x7d, 0x19, 0xd1, 0x01], "vextractf128 xmm1, ymm2, 0x1"); - test_instr(&[0xc4, 0xc3, 0x75, 0x38, 0x7c, 0x12, 0x05, 0x01], "vinserti128 ymm7, ymm1, [r10 + rdx * 1 + 0x5], 0x1"); - test_instr(&[0xc4, 0xc3, 0x75, 0x42, 0x7c, 0x12, 0x05, 0x61], "vmpsadbw ymm7, ymm1, [r10 + rdx * 1 + 0x5], 0x61"); - test_instr(&[0xc4, 0xc3, 0x75, 0x46, 0x7c, 0x12, 0x05, 0x61], "vperm2i128 ymm7, ymm1, [r10 + rdx * 1 + 0x5], 0x61"); - test_instr(&[0xc4, 0xc3, 0x75, 0x4a, 0x7c, 0x12, 0x05, 0x61], "vblendvps ymm7, ymm1, [r10 + rdx * 1 + 0x5], ymm6"); - test_instr(&[0xc4, 0xc3, 0x71, 0x4a, 0x7c, 0x12, 0x05, 0x61], "vblendvps xmm7, xmm1, [r10 + rdx * 1 + 0x5], xmm6"); + test_instr(&[0xc4, 0xc3, 0x75, 0x38, 0x7c, 0x12, 0x05, 0x01], "vinserti128 ymm7, ymm1, xmmword [r10 + rdx * 1 + 0x5], 0x1"); + test_instr(&[0xc4, 0xc3, 0x75, 0x42, 0x7c, 0x12, 0x05, 0x61], "vmpsadbw ymm7, ymm1, ymmword [r10 + rdx * 1 + 0x5], 0x61"); + test_instr(&[0xc4, 0xc3, 0x75, 0x46, 0x7c, 0x12, 0x05, 0x61], "vperm2i128 ymm7, ymm1, ymmword [r10 + rdx * 1 + 0x5], 0x61"); + test_instr(&[0xc4, 0xc3, 0x75, 0x4a, 0x7c, 0x12, 0x05, 0x61], "vblendvps ymm7, ymm1, ymmword [r10 + rdx * 1 + 0x5], ymm6"); + test_instr(&[0xc4, 0xc3, 0x71, 0x4a, 0x7c, 0x12, 0x05, 0x61], "vblendvps xmm7, xmm1, xmmword [r10 + rdx * 1 + 0x5], xmm6"); test_instr(&[0xc4, 0xc3, 0x71, 0x4a, 0xdc, 0x61], "vblendvps xmm3, xmm1, xmm12, xmm6"); - test_instr(&[0xc4, 0xc3, 0x75, 0x4b, 0x7c, 0x12, 0x05, 0x61], "vblendvpd ymm7, ymm1, [r10 + rdx * 1 + 0x5], ymm6"); - test_instr(&[0xc4, 0xc3, 0x71, 0x4b, 0x7c, 0x12, 0x05, 0x61], "vblendvpd xmm7, xmm1, [r10 + rdx * 1 + 0x5], xmm6"); + test_instr(&[0xc4, 0xc3, 0x75, 0x4b, 0x7c, 0x12, 0x05, 0x61], "vblendvpd ymm7, ymm1, ymmword [r10 + rdx * 1 + 0x5], ymm6"); + test_instr(&[0xc4, 0xc3, 0x71, 0x4b, 0x7c, 0x12, 0x05, 0x61], "vblendvpd xmm7, xmm1, xmmword [r10 + rdx * 1 + 0x5], xmm6"); test_instr(&[0xc4, 0xc3, 0x71, 0x4b, 0xdc, 0x61], "vblendvpd xmm3, xmm1, xmm12, xmm6"); - test_instr(&[0xc4, 0xc3, 0x71, 0x4c, 0x7c, 0x12, 0x05, 0x61], "vpblendvb xmm7, xmm1, [r10 + rdx * 1 + 0x5], xmm6"); + test_instr(&[0xc4, 0xc3, 0x71, 0x4c, 0x7c, 0x12, 0x05, 0x61], "vpblendvb xmm7, xmm1, xmmword [r10 + rdx * 1 + 0x5], xmm6"); - test_instr(&[0xc5, 0xc9, 0xf1, 0x0f], "vpsllw xmm1, xmm6, [rdi]"); + test_instr(&[0xc5, 0xc9, 0xf1, 0x0f], "vpsllw xmm1, xmm6, xmmword [rdi]"); test_instr(&[0xc5, 0xc9, 0xf1, 0xcf], "vpsllw xmm1, xmm6, xmm7"); - test_instr(&[0xc5, 0xcd, 0xf1, 0x0f], "vpsllw ymm1, ymm6, [rdi]"); + test_instr(&[0xc5, 0xcd, 0xf1, 0x0f], "vpsllw ymm1, ymm6, xmmword [rdi]"); test_instr(&[0xc5, 0xcd, 0xf1, 0xcf], "vpsllw ymm1, ymm6, xmm7"); - test_instr(&[0xc5, 0xc9, 0xf2, 0x0f], "vpslld xmm1, xmm6, [rdi]"); + test_instr(&[0xc5, 0xc9, 0xf2, 0x0f], "vpslld xmm1, xmm6, xmmword [rdi]"); test_instr(&[0xc5, 0xc9, 0xf2, 0xcf], "vpslld xmm1, xmm6, xmm7"); - test_instr(&[0xc5, 0xcd, 0xf2, 0x0f], "vpslld ymm1, ymm6, [rdi]"); + test_instr(&[0xc5, 0xcd, 0xf2, 0x0f], "vpslld ymm1, ymm6, xmmword [rdi]"); test_instr(&[0xc5, 0xcd, 0xf2, 0xcf], "vpslld ymm1, ymm6, xmm7"); - test_instr(&[0xc5, 0xc9, 0xf3, 0x0f], "vpsllq xmm1, xmm6, [rdi]"); + test_instr(&[0xc5, 0xc9, 0xf3, 0x0f], "vpsllq xmm1, xmm6, xmmword [rdi]"); test_instr(&[0xc5, 0xc9, 0xf3, 0xcf], "vpsllq xmm1, xmm6, xmm7"); - test_instr(&[0xc5, 0xcd, 0xf3, 0x0f], "vpsllq ymm1, ymm6, [rdi]"); + test_instr(&[0xc5, 0xcd, 0xf3, 0x0f], "vpsllq ymm1, ymm6, xmmword [rdi]"); test_instr(&[0xc5, 0xcd, 0xf3, 0xcf], "vpsllq ymm1, ymm6, xmm7"); test_instr(&[0xc5, 0xf1, 0xc4, 0xd8, 0x78], "vpinsrw xmm3, xmm1, eax, 0x78"); - test_instr(&[0xc5, 0xf1, 0xc4, 0x18, 0x78], "vpinsrw xmm3, xmm1, [rax], 0x78"); - - test_instr(&[0xc5, 0xe0, 0x54, 0x03], "vandps xmm0, xmm3, [rbx]"); - test_instr(&[0xc5, 0xe1, 0x54, 0x03], "vandpd xmm0, xmm3, [rbx]"); - test_instr(&[0xc5, 0xe0, 0x55, 0x03], "vandnps xmm0, xmm3, [rbx]"); - test_instr(&[0xc5, 0xe1, 0x55, 0x03], "vandnpd xmm0, xmm3, [rbx]"); - test_instr(&[0xc5, 0xe0, 0x56, 0x03], "vorps xmm0, xmm3, [rbx]"); - test_instr(&[0xc5, 0xe1, 0x56, 0x03], "vorpd xmm0, xmm3, [rbx]"); - test_instr(&[0xc4, 0xa2, 0x15, 0x3e, 0x14, 0xb9], "vpmaxuw ymm2, ymm13, [rcx + r15 * 4]"); + test_instr(&[0xc5, 0xf1, 0xc4, 0x18, 0x78], "vpinsrw xmm3, xmm1, word [rax], 0x78"); + + test_instr(&[0xc5, 0xe0, 0x54, 0x03], "vandps xmm0, xmm3, xmmword [rbx]"); + test_instr(&[0xc5, 0xe1, 0x54, 0x03], "vandpd xmm0, xmm3, xmmword [rbx]"); + test_instr(&[0xc5, 0xe0, 0x55, 0x03], "vandnps xmm0, xmm3, xmmword [rbx]"); + test_instr(&[0xc5, 0xe1, 0x55, 0x03], "vandnpd xmm0, xmm3, xmmword [rbx]"); + test_instr(&[0xc5, 0xe0, 0x56, 0x03], "vorps xmm0, xmm3, xmmword [rbx]"); + test_instr(&[0xc5, 0xe1, 0x56, 0x03], "vorpd xmm0, xmm3, xmmword [rbx]"); + test_instr(&[0xc4, 0xa2, 0x15, 0x3e, 0x14, 0xb9], "vpmaxuw ymm2, ymm13, ymmword [rcx + r15 * 4]"); } #[test] @@ -2684,34 +2502,34 @@ fn prefixed_0f() { test_display(&[0xf2, 0x0f, 0x06], "clts"); test_display(&[0x0f, 0x07], "sysret"); test_display(&[0xf2, 0x0f, 0x07], "sysret"); - test_display(&[0x0f, 0x12, 0x0f], "movlps xmm1, [rdi]"); + test_display(&[0x0f, 0x12, 0x0f], "movlps xmm1, qword [rdi]"); test_display(&[0x0f, 0x12, 0xcf], "movhlps xmm1, xmm7"); - test_display(&[0x0f, 0x16, 0x0f], "movhps xmm1, [rdi]"); + test_display(&[0x0f, 0x16, 0x0f], "movhps xmm1, qword [rdi]"); test_display(&[0x0f, 0x16, 0xcf], "movlhps xmm1, xmm7"); test_display(&[0x0f, 0x12, 0xc0], "movhlps xmm0, xmm0"); test_invalid(&[0x0f, 0x13, 0xc0]); - test_display(&[0x0f, 0x13, 0x00], "movlps [rax], xmm0"); - test_display(&[0x0f, 0x14, 0x08], "unpcklps xmm1, [rax]"); - test_display(&[0x0f, 0x15, 0x08], "unpckhps xmm1, [rax]"); - test_display(&[0x0f, 0x16, 0x0f], "movhps xmm1, [rdi]"); + test_display(&[0x0f, 0x13, 0x00], "movlps qword [rax], xmm0"); + test_display(&[0x0f, 0x14, 0x08], "unpcklps xmm1, xmmword [rax]"); + test_display(&[0x0f, 0x15, 0x08], "unpckhps xmm1, xmmword [rax]"); + test_display(&[0x0f, 0x16, 0x0f], "movhps xmm1, qword [rdi]"); test_display(&[0x0f, 0x16, 0xc0], "movlhps xmm0, xmm0"); test_invalid(&[0x0f, 0x17, 0xc0]); - test_display(&[0x0f, 0x17, 0x00], "movhps [rax], xmm0"); + test_display(&[0x0f, 0x17, 0x00], "movhps qword [rax], xmm0"); test_display(&[0x0f, 0x18, 0xc0], "nop eax"); // capstone says invalid, xed says nop - test_display(&[0x0f, 0x18, 0x00], "prefetchnta [rax]"); - test_display(&[0x0f, 0x18, 0x08], "prefetch0 [rax]"); - test_display(&[0x0f, 0x18, 0x10], "prefetch1 [rax]"); - test_display(&[0x0f, 0x18, 0x18], "prefetch2 [rax]"); - test_display(&[0x0f, 0x18, 0x20], "nop [rax]"); - test_display(&[0x4f, 0x0f, 0x18, 0x20], "nop [r8]"); + test_display(&[0x0f, 0x18, 0x00], "prefetchnta zmmword [rax]"); + test_display(&[0x0f, 0x18, 0x08], "prefetch0 zmmword [rax]"); + test_display(&[0x0f, 0x18, 0x10], "prefetch1 zmmword [rax]"); + test_display(&[0x0f, 0x18, 0x18], "prefetch2 zmmword [rax]"); + test_display(&[0x0f, 0x18, 0x20], "nop zmmword [rax]"); + test_display(&[0x4f, 0x0f, 0x18, 0x20], "nop zmmword [r8]"); test_display(&[0x0f, 0x18, 0xcc], "nop esp"); - test_display(&[0x0f, 0x19, 0x20], "nop [rax]"); - test_display(&[0x0f, 0x1a, 0x20], "nop [rax]"); - test_display(&[0x0f, 0x1b, 0x20], "nop [rax]"); - test_display(&[0x0f, 0x1c, 0x20], "nop [rax]"); - test_display(&[0x0f, 0x1d, 0x20], "nop [rax]"); - test_display(&[0x0f, 0x1e, 0x20], "nop [rax]"); - test_display(&[0x0f, 0x1f, 0x20], "nop [rax]"); + test_display(&[0x0f, 0x19, 0x20], "nop dword [rax]"); + test_display(&[0x0f, 0x1a, 0x20], "nop dword [rax]"); + test_display(&[0x0f, 0x1b, 0x20], "nop dword [rax]"); + test_display(&[0x0f, 0x1c, 0x20], "nop dword [rax]"); + test_display(&[0x0f, 0x1d, 0x20], "nop dword [rax]"); + test_display(&[0x0f, 0x1e, 0x20], "nop dword [rax]"); + test_display(&[0x0f, 0x1f, 0x20], "nop dword [rax]"); test_invalid(&[0x45, 0x0f, 0x20, 0xc8]); test_display(&[0x45, 0x0f, 0x20, 0xc0], "mov r8, cr8"); test_invalid(&[0x0f, 0x20, 0xc8]); @@ -2741,39 +2559,39 @@ fn prefixed_0f() { test_invalid(&[0x66, 0x0f, 0x37]); test_invalid(&[0xf2, 0x0f, 0x37]); test_invalid(&[0xf3, 0x0f, 0x37]); - test_display(&[0x0f, 0x60, 0x00], "punpcklbw mm0, [rax]"); + test_display(&[0x0f, 0x60, 0x00], "punpcklbw mm0, dword [rax]"); test_display(&[0x0f, 0x60, 0xc2], "punpcklbw mm0, mm2"); - test_display(&[0x0f, 0x61, 0x00], "punpcklwd mm0, [rax]"); + test_display(&[0x0f, 0x61, 0x00], "punpcklwd mm0, dword [rax]"); test_display(&[0x0f, 0x61, 0xc2], "punpcklwd mm0, mm2"); - test_display(&[0x0f, 0x62, 0x00], "punpckldq mm0, [rax]"); + test_display(&[0x0f, 0x62, 0x00], "punpckldq mm0, dword [rax]"); test_display(&[0x0f, 0x62, 0xc2], "punpckldq mm0, mm2"); - test_display(&[0x0f, 0x63, 0x00], "packsswb mm0, [rax]"); + test_display(&[0x0f, 0x63, 0x00], "packsswb mm0, qword [rax]"); test_display(&[0x0f, 0x63, 0xc2], "packsswb mm0, mm2"); - test_display(&[0x0f, 0x64, 0x00], "pcmpgtb mm0, [rax]"); + test_display(&[0x0f, 0x64, 0x00], "pcmpgtb mm0, qword [rax]"); test_display(&[0x0f, 0x64, 0xc2], "pcmpgtb mm0, mm2"); - test_display(&[0x0f, 0x65, 0x00], "pcmpgtw mm0, [rax]"); + test_display(&[0x0f, 0x65, 0x00], "pcmpgtw mm0, qword [rax]"); test_display(&[0x0f, 0x65, 0xc2], "pcmpgtw mm0, mm2"); - test_display(&[0x0f, 0x66, 0x00], "pcmpgtd mm0, [rax]"); + test_display(&[0x0f, 0x66, 0x00], "pcmpgtd mm0, qword [rax]"); test_display(&[0x0f, 0x66, 0xc2], "pcmpgtd mm0, mm2"); - test_display(&[0x0f, 0x67, 0x00], "packuswb mm0, [rax]"); + test_display(&[0x0f, 0x67, 0x00], "packuswb mm0, qword [rax]"); test_display(&[0x0f, 0x67, 0xc2], "packuswb mm0, mm2"); - test_display(&[0x0f, 0x68, 0x00], "punpckhbw mm0, [rax]"); + test_display(&[0x0f, 0x68, 0x00], "punpckhbw mm0, qword [rax]"); test_display(&[0x0f, 0x68, 0xc2], "punpckhbw mm0, mm2"); - test_display(&[0x0f, 0x69, 0x00], "punpckhwd mm0, [rax]"); + test_display(&[0x0f, 0x69, 0x00], "punpckhwd mm0, qword [rax]"); test_display(&[0x0f, 0x69, 0xc2], "punpckhwd mm0, mm2"); - test_display(&[0x0f, 0x6a, 0x00], "punpckhdq mm0, [rax]"); + test_display(&[0x0f, 0x6a, 0x00], "punpckhdq mm0, qword [rax]"); test_display(&[0x0f, 0x6a, 0xc2], "punpckhdq mm0, mm2"); - test_display(&[0x0f, 0x6b, 0x00], "packssdw mm0, [rax]"); + test_display(&[0x0f, 0x6b, 0x00], "packssdw mm0, qword [rax]"); test_display(&[0x0f, 0x6b, 0xc2], "packssdw mm0, mm2"); test_invalid(&[0x0f, 0x6c]); test_invalid(&[0x0f, 0x6d]); - test_display(&[0x0f, 0x6e, 0x00], "movd mm0, [rax]"); + test_display(&[0x0f, 0x6e, 0x00], "movd mm0, dword [rax]"); test_display(&[0x0f, 0x6e, 0xc2], "movd mm0, edx"); - test_display(&[0x0f, 0x6f, 0x00], "movq mm0, [rax]"); + test_display(&[0x0f, 0x6f, 0x00], "movq mm0, qword [rax]"); test_display(&[0x0f, 0x6f, 0xc2], "movq mm0, mm2"); test_display(&[0x0f, 0x6f, 0xfb], "movq mm7, mm3"); - test_display(&[0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, [rax], 0x7f"); - test_display(&[0x4f, 0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, [r8], 0x7f"); + test_display(&[0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [rax], 0x7f"); + test_display(&[0x4f, 0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [r8], 0x7f"); test_invalid(&[0x0f, 0x71, 0x00, 0x7f]); test_invalid(&[0x0f, 0x71, 0xc0, 0x7f]); test_display(&[0x0f, 0x71, 0xd0, 0x7f], "psrlw mm0, 0x7f"); @@ -2830,16 +2648,16 @@ fn prefixed_f30f() { #[test] fn test_adx() { test_display(&[0x66, 0x0f, 0x38, 0xf6, 0xc1], "adcx eax, ecx"); - test_display(&[0x66, 0x0f, 0x38, 0xf6, 0x01], "adcx eax, [rcx]"); - test_display(&[0x66, 0x4f, 0x0f, 0x38, 0xf6, 0x01], "adcx r8, [r9]"); + test_display(&[0x66, 0x0f, 0x38, 0xf6, 0x01], "adcx eax, dword [rcx]"); + test_display(&[0x66, 0x4f, 0x0f, 0x38, 0xf6, 0x01], "adcx r8, qword [r9]"); test_display(&[0xf3, 0x0f, 0x38, 0xf6, 0xc1], "adox eax, ecx"); - test_display(&[0xf3, 0x0f, 0x38, 0xf6, 0x01], "adox eax, [rcx]"); - test_display(&[0xf3, 0x4f, 0x0f, 0x38, 0xf6, 0x01], "adox r8, [r9]"); + test_display(&[0xf3, 0x0f, 0x38, 0xf6, 0x01], "adox eax, dword [rcx]"); + test_display(&[0xf3, 0x4f, 0x0f, 0x38, 0xf6, 0x01], "adox r8, qword [r9]"); } #[test] fn test_prefetchw() { - test_display(&[0x0f, 0x0d, 0x08], "prefetchw [rax]"); + test_display(&[0x0f, 0x0d, 0x08], "prefetchw zmmword [rax]"); } #[test] @@ -2861,20 +2679,20 @@ fn test_svm() { test_display(&[0x0f, 0x01, 0xd8], "vmrun rax"); test_display(&[0x0f, 0x78, 0xc4], "vmread rsp, rax"); test_display(&[0x0f, 0x79, 0xc5], "vmwrite rax, rbp"); - test_display(&[0x0f, 0x78, 0x0b], "vmread [rbx], rcx"); + test_display(&[0x0f, 0x78, 0x0b], "vmread qword [rbx], rcx"); test_invalid(&[0x66, 0x0f, 0x78, 0x03]); - test_display(&[0x0f, 0x79, 0x0b], "vmwrite rcx, [rbx]"); + test_display(&[0x0f, 0x79, 0x0b], "vmwrite rcx, qword [rbx]"); test_invalid(&[0x66, 0x0f, 0x79, 0x03]); } #[test] fn test_movbe() { - test_display(&[0x0f, 0x38, 0xf0, 0x06], "movbe eax, [rsi]"); - test_display(&[0x4f, 0x0f, 0x38, 0xf0, 0x06], "movbe r8, [r14]"); + test_display(&[0x0f, 0x38, 0xf0, 0x06], "movbe eax, dword [rsi]"); + test_display(&[0x4f, 0x0f, 0x38, 0xf0, 0x06], "movbe r8, qword [r14]"); test_invalid(&[0x4f, 0x0f, 0x38, 0xf0, 0xc6]); - test_display(&[0x0f, 0x38, 0xf1, 0x06], "movbe [rsi], eax"); - test_display(&[0x4f, 0x0f, 0x38, 0xf1, 0x06], "movbe [r14], r8"); - test_display(&[0x66, 0x0f, 0x38, 0xf1, 0x06], "movbe [rsi], ax"); + test_display(&[0x0f, 0x38, 0xf1, 0x06], "movbe dword [rsi], eax"); + test_display(&[0x4f, 0x0f, 0x38, 0xf1, 0x06], "movbe qword [r14], r8"); + test_display(&[0x66, 0x0f, 0x38, 0xf1, 0x06], "movbe word [rsi], ax"); test_invalid(&[0x66, 0x0f, 0x38, 0xf1, 0xc6]); } @@ -2899,30 +2717,30 @@ fn test_rand() { #[test] fn test_sha() { - test_display(&[0x0f, 0x3a, 0xcc, 0x12, 0x40], "sha1rnds4 xmm2, [rdx], 0x40"); - test_display(&[0x0f, 0x3a, 0xcc, 0x12, 0xff], "sha1rnds4 xmm2, [rdx], 0xff"); - test_display(&[0x0f, 0x38, 0xc8, 0x12], "sha1nexte xmm2, [rdx]"); - test_display(&[0x0f, 0x38, 0xc9, 0x12], "sha1msg1 xmm2, [rdx]"); - test_display(&[0x0f, 0x38, 0xca, 0x12], "sha1msg2 xmm2, [rdx]"); - test_display(&[0x0f, 0x38, 0xcb, 0x12], "sha256rnds2 xmm2, [rdx]"); - test_display(&[0x0f, 0x38, 0xcc, 0x12], "sha256msg1 xmm2, [rdx]"); - test_display(&[0x0f, 0x38, 0xcd, 0x12], "sha256msg2 xmm2, [rdx]"); + test_display(&[0x0f, 0x3a, 0xcc, 0x12, 0x40], "sha1rnds4 xmm2, xmmword [rdx], 0x40"); + test_display(&[0x0f, 0x3a, 0xcc, 0x12, 0xff], "sha1rnds4 xmm2, xmmword [rdx], 0xff"); + test_display(&[0x0f, 0x38, 0xc8, 0x12], "sha1nexte xmm2, xmmword [rdx]"); + test_display(&[0x0f, 0x38, 0xc9, 0x12], "sha1msg1 xmm2, xmmword [rdx]"); + test_display(&[0x0f, 0x38, 0xca, 0x12], "sha1msg2 xmm2, xmmword [rdx]"); + test_display(&[0x0f, 0x38, 0xcb, 0x12], "sha256rnds2 xmm2, xmmword [rdx]"); + test_display(&[0x0f, 0x38, 0xcc, 0x12], "sha256msg1 xmm2, xmmword [rdx]"); + test_display(&[0x0f, 0x38, 0xcd, 0x12], "sha256msg2 xmm2, xmmword [rdx]"); } #[test] fn test_vmx() { - test_display(&[0x0f, 0xc7, 0x3f], "vmptrst [rdi]"); - test_display(&[0x0f, 0xc7, 0x37], "vmptrld [rdi]"); - test_display(&[0xf3, 0x0f, 0xc7, 0x37], "vmxon [rdi]"); + test_display(&[0x0f, 0xc7, 0x3f], "vmptrst qword [rdi]"); + test_display(&[0x0f, 0xc7, 0x37], "vmptrld qword [rdi]"); + test_display(&[0xf3, 0x0f, 0xc7, 0x37], "vmxon qword [rdi]"); test_display(&[0x66, 0x0f, 0xc7, 0xf7], "rdrand di"); - test_display(&[0x66, 0x0f, 0xc7, 0x37], "vmclear [rdi]"); + test_display(&[0x66, 0x0f, 0xc7, 0x37], "vmclear qword [rdi]"); // this is actually vmx // test_invalid(&[0x66, 0x0f, 0xc7, 0x03]); - test_display(&[0x66, 0x4f, 0x0f, 0xc7, 0x33], "vmclear [r11]"); - test_display(&[0x66, 0x0f, 0xc7, 0x33], "vmclear [rbx]"); - test_display(&[0xf3, 0x4f, 0x0f, 0xc7, 0x33], "vmxon [r11]"); - test_display(&[0xf3, 0x0f, 0xc7, 0x33], "vmxon [rbx]"); + test_display(&[0x66, 0x4f, 0x0f, 0xc7, 0x33], "vmclear qword [r11]"); + test_display(&[0x66, 0x0f, 0xc7, 0x33], "vmclear qword [rbx]"); + test_display(&[0xf3, 0x4f, 0x0f, 0xc7, 0x33], "vmxon qword [r11]"); + test_display(&[0xf3, 0x0f, 0xc7, 0x33], "vmxon qword [rbx]"); } #[test] @@ -2932,34 +2750,34 @@ fn test_rdpid() { #[test] fn test_cmpxchg8b() { - test_display(&[0x0f, 0xc7, 0x0f], "cmpxchg8b [rdi]"); - test_display(&[0xf2, 0x0f, 0xc7, 0x0f], "cmpxchg8b [rdi]"); - test_display(&[0xf3, 0x0f, 0xc7, 0x0f], "cmpxchg8b [rdi]"); - test_display(&[0x66, 0x0f, 0xc7, 0x0f], "cmpxchg8b [rdi]"); - test_display(&[0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b [r15]"); - test_display(&[0xf2, 0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b [r15]"); - test_display(&[0xf3, 0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b [r15]"); - test_display(&[0x66, 0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b [r15]"); + test_display(&[0x0f, 0xc7, 0x0f], "cmpxchg8b qword [rdi]"); + test_display(&[0xf2, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [rdi]"); + test_display(&[0xf3, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [rdi]"); + test_display(&[0x66, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [rdi]"); + test_display(&[0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b xmmword [r15]"); + test_display(&[0xf2, 0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b xmmword [r15]"); + test_display(&[0xf3, 0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b xmmword [r15]"); + test_display(&[0x66, 0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b xmmword [r15]"); } #[test] fn test_x87() { // test_display(&[0xd8, 0x03], "fadd st, dword ptr [rbx]"); - test_display(&[0xd8, 0x03], "fadd st(0), [rbx]"); + test_display(&[0xd8, 0x03], "fadd st(0), dword [rbx]"); // test_display(&[0xd8, 0x0b], "fmul st, dword ptr [rbx]"); - test_display(&[0xd8, 0x0b], "fmul st(0), [rbx]"); + test_display(&[0xd8, 0x0b], "fmul st(0), dword [rbx]"); // test_display(&[0xd8, 0x13], "fcom st, dword ptr [rbx]"); - test_display(&[0xd8, 0x13], "fcom st(0), [rbx]"); + test_display(&[0xd8, 0x13], "fcom st(0), dword [rbx]"); // test_display(&[0xd8, 0x1b], "fcomp st, dword ptr [rbx]"); - test_display(&[0xd8, 0x1b], "fcomp st(0), [rbx]"); + test_display(&[0xd8, 0x1b], "fcomp st(0), dword [rbx]"); // test_display(&[0xd8, 0x23], "fsub st, dword ptr [rbx]"); - test_display(&[0xd8, 0x23], "fsub st(0), [rbx]"); + test_display(&[0xd8, 0x23], "fsub st(0), dword [rbx]"); // test_display(&[0xd8, 0x2b], "fsubr st, dword ptr [rbx]"); - test_display(&[0xd8, 0x2b], "fsubr st(0), [rbx]"); + test_display(&[0xd8, 0x2b], "fsubr st(0), dword [rbx]"); // test_display(&[0xd8, 0x33], "fdiv st, dword ptr [rbx]"); - test_display(&[0xd8, 0x33], "fdiv st(0), [rbx]"); + test_display(&[0xd8, 0x33], "fdiv st(0), dword [rbx]"); // test_display(&[0xd8, 0x3b], "fdivr st, dword ptr [rbx]"); - test_display(&[0xd8, 0x3b], "fdivr st(0), [rbx]"); + test_display(&[0xd8, 0x3b], "fdivr st(0), dword [rbx]"); // test_display(&[0xd8, 0xc3], "fadd st, st(3)"); test_display(&[0xd8, 0xc3], "fadd st(0), st(3)"); // test_display(&[0xd8, 0xcb], "fmul st, st(3)"); @@ -2977,7 +2795,7 @@ fn test_x87() { // test_display(&[0xd8, 0xfb], "fdivr st, st(3)"); test_display(&[0xd8, 0xfb], "fdivr st(0), st(3)"); // test_display(&[0xd9, 0x03], "fld st, dword ptr [rbx]"); - test_display(&[0xd9, 0x03], "fld st(0), [rbx]"); + test_display(&[0xd9, 0x03], "fld st(0), dword [rbx]"); test_invalid(&[0xd9, 0x08]); test_invalid(&[0xd9, 0x09]); test_invalid(&[0xd9, 0x0a]); @@ -2987,17 +2805,17 @@ fn test_x87() { test_invalid(&[0xd9, 0x0e]); test_invalid(&[0xd9, 0x0f]); // test_display(&[0xd9, 0x13], "fst dword ptr [rbx], st"); - test_display(&[0xd9, 0x13], "fst [rbx], st(0)"); + test_display(&[0xd9, 0x13], "fst dword [rbx], st(0)"); // test_display(&[0xd9, 0x1b], "fstp dword ptr [rbx], st"); - test_display(&[0xd9, 0x1b], "fstp [rbx], st(0)"); + test_display(&[0xd9, 0x1b], "fstp dword [rbx], st(0)"); // test_display(&[0xd9, 0x23], "fldenv ptr [rbx]"); - test_display(&[0xd9, 0x23], "fldenv [rbx]"); + test_display(&[0xd9, 0x23], "fldenv ptr [rbx]"); // test_display(&[0xd9, 0x2b], "fldcw word ptr [rbx]"); - test_display(&[0xd9, 0x2b], "fldcw [rbx]"); + test_display(&[0xd9, 0x2b], "fldcw word [rbx]"); // test_display(&[0xd9, 0x33], "fnstenv ptr [rbx]"); - test_display(&[0xd9, 0x33], "fnstenv [rbx]"); + test_display(&[0xd9, 0x33], "fnstenv ptr [rbx]"); // test_display(&[0xd9, 0x3b], "fnstcw word ptr [rbx]"); - test_display(&[0xd9, 0x3b], "fnstcw [rbx]"); + test_display(&[0xd9, 0x3b], "fnstcw word [rbx]"); // test_display(&[0xd9, 0xc3], "fld st, st(3)"); test_display(&[0xd9, 0xc3], "fld st(0), st(3)"); // test_display(&[0xd9, 0xcb], "fxch st, st(3)"); @@ -3046,21 +2864,21 @@ fn test_x87() { test_display(&[0xd9, 0xfe], "fsin"); test_display(&[0xd9, 0xff], "fcos"); // test_display(&[0xda, 0x03], "fiadd st, dword ptr [rbx]"); - test_display(&[0xda, 0x03], "fiadd st(0), [rbx]"); + test_display(&[0xda, 0x03], "fiadd st(0), dword [rbx]"); // test_display(&[0xda, 0x0b], "fimul st, dword ptr [rbx]"); - test_display(&[0xda, 0x0b], "fimul st(0), [rbx]"); + test_display(&[0xda, 0x0b], "fimul st(0), dword [rbx]"); // test_display(&[0xda, 0x13], "ficom st, dword ptr [rbx]"); - test_display(&[0xda, 0x13], "ficom st(0), [rbx]"); + test_display(&[0xda, 0x13], "ficom st(0), dword [rbx]"); // test_display(&[0xda, 0x1b], "ficomp st, dword ptr [rbx]"); - test_display(&[0xda, 0x1b], "ficomp st(0), [rbx]"); + test_display(&[0xda, 0x1b], "ficomp st(0), dword [rbx]"); // test_display(&[0xda, 0x23], "fisub st, dword ptr [rbx]"); - test_display(&[0xda, 0x23], "fisub st(0), [rbx]"); + test_display(&[0xda, 0x23], "fisub st(0), dword [rbx]"); // test_display(&[0xda, 0x2b], "fisubr st, dword ptr [rbx]"); - test_display(&[0xda, 0x2b], "fisubr st(0), [rbx]"); + test_display(&[0xda, 0x2b], "fisubr st(0), dword [rbx]"); // test_display(&[0xda, 0x33], "fidiv st, dword ptr [rbx]"); - test_display(&[0xda, 0x33], "fidiv st(0), [rbx]"); + test_display(&[0xda, 0x33], "fidiv st(0), dword [rbx]"); // test_display(&[0xda, 0x3b], "fidivr st, dword ptr [rbx]"); - test_display(&[0xda, 0x3b], "fidivr st(0), [rbx]"); + test_display(&[0xda, 0x3b], "fidivr st(0), dword [rbx]"); // test_display(&[0xda, 0xc3], "fcmovb st, st(3)"); test_display(&[0xda, 0xc3], "fcmovb st(0), st(3)"); // test_display(&[0xda, 0xcb], "fcmove st, st(3)"); @@ -3102,13 +2920,13 @@ fn test_x87() { test_invalid(&[0xda, 0xfe]); test_invalid(&[0xda, 0xff]); // test_display(&[0xdb, 0x03], "fild st, dword ptr [rbx]"); - test_display(&[0xdb, 0x03], "fild st(0), [rbx]"); + test_display(&[0xdb, 0x03], "fild st(0), dword [rbx]"); // test_display(&[0xdb, 0x0b], "fisttp dword ptr [rbx], st"); - test_display(&[0xdb, 0x0b], "fisttp [rbx], st(0)"); + test_display(&[0xdb, 0x0b], "fisttp dword [rbx], st(0)"); // test_display(&[0xdb, 0x13], "fist dword ptr [rbx], st"); - test_display(&[0xdb, 0x13], "fist [rbx], st(0)"); + test_display(&[0xdb, 0x13], "fist dword [rbx], st(0)"); // test_display(&[0xdb, 0x1b], "fistp dword ptr [rbx], st"); - test_display(&[0xdb, 0x1b], "fistp [rbx], st(0)"); + test_display(&[0xdb, 0x1b], "fistp dword [rbx], st(0)"); test_invalid(&[0xdb, 0x20]); test_invalid(&[0xdb, 0x21]); test_invalid(&[0xdb, 0x22]); @@ -3118,7 +2936,7 @@ fn test_x87() { test_invalid(&[0xdb, 0x26]); test_invalid(&[0xdb, 0x27]); // test_display(&[0xdb, 0x2b], "fld st, ptr [rbx]"); - test_display(&[0xdb, 0x2b], "fld st(0), [rbx]"); + test_display(&[0xdb, 0x2b], "fld st(0), mword [rbx]"); test_invalid(&[0xdb, 0x30]); test_invalid(&[0xdb, 0x31]); test_invalid(&[0xdb, 0x32]); @@ -3128,7 +2946,7 @@ fn test_x87() { test_invalid(&[0xdb, 0x36]); test_invalid(&[0xdb, 0x37]); // test_display(&[0xdb, 0x3b], "fstp ptr [rbx], st"); - test_display(&[0xdb, 0x3b], "fstp [rbx], st(0)"); + test_display(&[0xdb, 0x3b], "fstp mword [rbx], st(0)"); // test_display(&[0xdb, 0xc3], "fcmovnb st, st(3)"); test_display(&[0xdb, 0xc3], "fcmovnb st(0), st(3)"); // test_display(&[0xdb, 0xcb], "fcmovne st, st(3)"); @@ -3158,21 +2976,21 @@ fn test_x87() { test_invalid(&[0xdb, 0xfe]); test_invalid(&[0xdb, 0xff]); // test_display(&[0xdc, 0x03], "fadd st, qword ptr [rbx]"); - test_display(&[0xdc, 0x03], "fadd st(0), [rbx]"); + test_display(&[0xdc, 0x03], "fadd st(0), qword [rbx]"); // test_display(&[0xdc, 0x0b], "fmul st, qword ptr [rbx]"); - test_display(&[0xdc, 0x0b], "fmul st(0), [rbx]"); + test_display(&[0xdc, 0x0b], "fmul st(0), qword [rbx]"); // test_display(&[0xdc, 0x13], "fcom st, qword ptr [rbx]"); - test_display(&[0xdc, 0x13], "fcom st(0), [rbx]"); + test_display(&[0xdc, 0x13], "fcom st(0), qword [rbx]"); // test_display(&[0xdc, 0x1b], "fcomp st, qword ptr [rbx]"); - test_display(&[0xdc, 0x1b], "fcomp st(0), [rbx]"); + test_display(&[0xdc, 0x1b], "fcomp st(0), qword [rbx]"); // test_display(&[0xdc, 0x23], "fsub st, qword ptr [rbx]"); - test_display(&[0xdc, 0x23], "fsub st(0), [rbx]"); + test_display(&[0xdc, 0x23], "fsub st(0), qword [rbx]"); // test_display(&[0xdc, 0x2b], "fsubr st, qword ptr [rbx]"); - test_display(&[0xdc, 0x2b], "fsubr st(0), [rbx]"); + test_display(&[0xdc, 0x2b], "fsubr st(0), qword [rbx]"); // test_display(&[0xdc, 0x33], "fdiv st, qword ptr [rbx]"); - test_display(&[0xdc, 0x33], "fdiv st(0), [rbx]"); + test_display(&[0xdc, 0x33], "fdiv st(0), qword [rbx]"); // test_display(&[0xdc, 0x3b], "fdivr st, qword ptr [rbx]"); - test_display(&[0xdc, 0x3b], "fdivr st(0), [rbx]"); + test_display(&[0xdc, 0x3b], "fdivr st(0), qword [rbx]"); // test_display(&[0xdc, 0xc3], "fadd st(3), st"); test_display(&[0xdc, 0xc3], "fadd st(3), st(0)"); // test_display(&[0xdc, 0xcb], "fmul st(3), st"); @@ -3190,15 +3008,15 @@ fn test_x87() { // test_display(&[0xdc, 0xfb], "fdiv st(3), st"); test_display(&[0xdc, 0xfb], "fdiv st(3), st(0)"); // test_display(&[0xdd, 0x03], "fld st, qword ptr [rbx]"); - test_display(&[0xdd, 0x03], "fld st(0), [rbx]"); + test_display(&[0xdd, 0x03], "fld st(0), qword [rbx]"); // test_display(&[0xdd, 0x0b], "fisttp qword ptr [rbx], st"); - test_display(&[0xdd, 0x0b], "fisttp [rbx], st(0)"); + test_display(&[0xdd, 0x0b], "fisttp qword [rbx], st(0)"); // test_display(&[0xdd, 0x13], "fst qword ptr [rbx], st"); - test_display(&[0xdd, 0x13], "fst [rbx], st(0)"); + test_display(&[0xdd, 0x13], "fst qword [rbx], st(0)"); // test_display(&[0xdd, 0x1b], "fstp qword ptr [rbx], st"); - test_display(&[0xdd, 0x1b], "fstp [rbx], st(0)"); + test_display(&[0xdd, 0x1b], "fstp qword [rbx], st(0)"); // test_display(&[0xdd, 0x23], "frstor ptr [rbx]"); - test_display(&[0xdd, 0x23], "frstor [rbx]"); + test_display(&[0xdd, 0x23], "frstor ptr [rbx]"); test_invalid(&[0xdd, 0x28]); test_invalid(&[0xdd, 0x29]); test_invalid(&[0xdd, 0x2a]); @@ -3208,9 +3026,9 @@ fn test_x87() { test_invalid(&[0xdd, 0x2e]); test_invalid(&[0xdd, 0x2f]); // test_display(&[0xdd, 0x33], "fnsave ptr [rbx]"); - test_display(&[0xdd, 0x33], "fnsave [rbx]"); + test_display(&[0xdd, 0x33], "fnsave ptr [rbx]"); // test_display(&[0xdd, 0x3b], "fnstsw word ptr [rbx]"); - test_display(&[0xdd, 0x3b], "fnstsw [rbx]"); + test_display(&[0xdd, 0x3b], "fnstsw word [rbx]"); test_display(&[0xdd, 0xc3], "ffree st(3)"); // test_display(&[0xdd, 0xcb], "fxch st, st(3)"); test_display(&[0xdd, 0xcb], "fxch st(0), st(3)"); @@ -3239,21 +3057,21 @@ fn test_x87() { test_invalid(&[0xdd, 0xfe]); test_invalid(&[0xdd, 0xff]); // test_display(&[0xde, 0x03], "fiadd st, word ptr [rbx]"); - test_display(&[0xde, 0x03], "fiadd st(0), [rbx]"); + test_display(&[0xde, 0x03], "fiadd st(0), word [rbx]"); // test_display(&[0xde, 0x0b], "fimul st, word ptr [rbx]"); - test_display(&[0xde, 0x0b], "fimul st(0), [rbx]"); + test_display(&[0xde, 0x0b], "fimul st(0), word [rbx]"); // test_display(&[0xde, 0x13], "ficom st, word ptr [rbx]"); - test_display(&[0xde, 0x13], "ficom st(0), [rbx]"); + test_display(&[0xde, 0x13], "ficom st(0), word [rbx]"); // test_display(&[0xde, 0x1b], "ficomp st, word ptr [rbx]"); - test_display(&[0xde, 0x1b], "ficomp st(0), [rbx]"); + test_display(&[0xde, 0x1b], "ficomp st(0), word [rbx]"); // test_display(&[0xde, 0x23], "fisub st, word ptr [rbx]"); - test_display(&[0xde, 0x23], "fisub st(0), [rbx]"); + test_display(&[0xde, 0x23], "fisub st(0), word [rbx]"); // test_display(&[0xde, 0x2b], "fisubr st, word ptr [rbx]"); - test_display(&[0xde, 0x2b], "fisubr st(0), [rbx]"); + test_display(&[0xde, 0x2b], "fisubr st(0), word [rbx]"); // test_display(&[0xde, 0x33], "fidiv st, word ptr [rbx]"); - test_display(&[0xde, 0x33], "fidiv st(0), [rbx]"); + test_display(&[0xde, 0x33], "fidiv st(0), word [rbx]"); // test_display(&[0xde, 0x3b], "fidivr st, word ptr [rbx]"); - test_display(&[0xde, 0x3b], "fidivr st(0), [rbx]"); + test_display(&[0xde, 0x3b], "fidivr st(0), word [rbx]"); // test_display(&[0xde, 0xc3], "faddp st(3), st"); test_display(&[0xde, 0xc3], "faddp st(3), st(0)"); // test_display(&[0xde, 0xcb], "fmulp st(3), st"); @@ -3277,21 +3095,21 @@ fn test_x87() { // test_display(&[0xde, 0xfb], "fdivp st(3), st"); test_display(&[0xde, 0xfb], "fdivp st(3), st(0)"); // test_display(&[0xdf, 0x03], "fild st, word ptr [rbx]"); - test_display(&[0xdf, 0x03], "fild st(0), [rbx]"); + test_display(&[0xdf, 0x03], "fild st(0), word [rbx]"); // test_display(&[0xdf, 0x0b], "fisttp word ptr [rbx], st"); - test_display(&[0xdf, 0x0b], "fisttp [rbx], st(0)"); + test_display(&[0xdf, 0x0b], "fisttp word [rbx], st(0)"); // test_display(&[0xdf, 0x13], "fist word ptr [rbx], st"); - test_display(&[0xdf, 0x13], "fist [rbx], st(0)"); + test_display(&[0xdf, 0x13], "fist word [rbx], st(0)"); // test_display(&[0xdf, 0x1b], "fistp word ptr [rbx], st"); - test_display(&[0xdf, 0x1b], "fistp [rbx], st(0)"); + test_display(&[0xdf, 0x1b], "fistp word [rbx], st(0)"); // test_display(&[0xdf, 0x23], "fbld st, ptr [rbx]"); - test_display(&[0xdf, 0x23], "fbld st(0), [rbx]"); + test_display(&[0xdf, 0x23], "fbld st(0), mword [rbx]"); // test_display(&[0xdf, 0x2b], "fild st, qword ptr [rbx]"); - test_display(&[0xdf, 0x2b], "fild st(0), [rbx]"); + test_display(&[0xdf, 0x2b], "fild st(0), qword [rbx]"); // test_display(&[0xdf, 0x33], "fbstp ptr [rbx], st"); - test_display(&[0xdf, 0x33], "fbstp [rbx], st(0)"); + test_display(&[0xdf, 0x33], "fbstp mword [rbx], st(0)"); // test_display(&[0xdf, 0x3b], "fistp qword ptr [rbx], st"); - test_display(&[0xdf, 0x3b], "fistp [rbx], st(0)"); + test_display(&[0xdf, 0x3b], "fistp qword [rbx], st(0)"); // test_display(&[0xdf, 0xc3], "ffreep st(3)"); test_display(&[0xdf, 0xc3], "ffreep st(3)"); // test_display(&[0xdf, 0xcb], "fxch st, st(3)"); @@ -3326,7 +3144,7 @@ fn test_x87() { fn test_mishegos_finds() { test_display(&[0x65, 0x67, 0x65, 0x65, 0x0f, 0x0e], "femms"); test_display(&[0x26, 0x66, 0x67, 0x41, 0x0f, 0x38, 0xdf, 0xe4], "aesdeclast xmm4, xmm12"); - test_display(&[0x65, 0x66, 0x66, 0x64, 0x48, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, fs:[rdi]"); + test_display(&[0x65, 0x66, 0x66, 0x64, 0x48, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword fs:[rdi]"); test_invalid(&[0xf3, 0xf2, 0x41, 0x0f, 0xae, 0x8f, 0x54, 0x3c, 0x58, 0xb7]); /* test_display(&[652e662e0f3814ff], "blendvps"); @@ -3337,31 +3155,31 @@ fn test_mishegos_finds() { // impossible instruction if operands could be read: lock is illegal here. // test_display(&[f06565f2640f16], "???"); // test_display(&[0x0f, 0x38, 0xf6, 0x8c, 0x98, 0x4d, 0x33, 0xf5, 0xd3, ], "wrssd"); - test_display(&[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], "pi2fw mm6, [rax - 0x5]"); - test_display(&[0x0f, 0xc7, 0x0f], "cmpxchg8b [rdi]"); - test_display(&[0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b [r15]"); - test_display(&[0x66, 0x3e, 0x26, 0x2e, 0x2e, 0x0f, 0x38, 0x2a, 0x2b, ], "movntdqa xmm5, [rbx]"); - test_display(&[0x66, 0x2e, 0x67, 0x0f, 0x3a, 0x0d, 0xb8, 0xf0, 0x2f, 0x7c, 0xf0, 0x63, ], "blendpd xmm7, [eax - 0xf83d010], 0x63"); - test_display(&[0x66, 0x66, 0x64, 0x3e, 0x0f, 0x38, 0x23, 0x9d, 0x69, 0x0f, 0xa8, 0x2d, ], "pmovsxwd xmm3, fs:[rbp + 0x2da80f69]"); - test_display(&[0x2e, 0x66, 0x26, 0x64, 0x49, 0x0f, 0x3a, 0x21, 0x0b, 0xb1, ], "insertps xmm1, fs:[r11], -0x4f"); - test_display(&[0x66, 0x26, 0x45, 0x0f, 0x3a, 0x42, 0x96, 0x74, 0x29, 0x96, 0xf9, 0x6a], "mpsadbw xmm10, [r14 - 0x669d68c], 0x6a"); - test_display(&[0x67, 0x26, 0x66, 0x65, 0x0f, 0x38, 0x3f, 0x9d, 0xcc, 0x03, 0xb3, 0xfa], "pmaxud xmm3, gs:[ebp - 0x54cfc34]"); - test_display(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e, ], "movdiri [rbp + 0x3e], edx"); - test_display(&[0x36, 0x26, 0x66, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b rbp, [rbp + 0x729080b]"); + test_display(&[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], "pi2fw mm6, qword [rax - 0x5]"); + test_display(&[0x0f, 0xc7, 0x0f], "cmpxchg8b qword [rdi]"); + test_display(&[0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b xmmword [r15]"); + test_display(&[0x66, 0x3e, 0x26, 0x2e, 0x2e, 0x0f, 0x38, 0x2a, 0x2b, ], "movntdqa xmm5, xmmword [rbx]"); + test_display(&[0x66, 0x2e, 0x67, 0x0f, 0x3a, 0x0d, 0xb8, 0xf0, 0x2f, 0x7c, 0xf0, 0x63, ], "blendpd xmm7, xmmword [eax - 0xf83d010], 0x63"); + test_display(&[0x66, 0x66, 0x64, 0x3e, 0x0f, 0x38, 0x23, 0x9d, 0x69, 0x0f, 0xa8, 0x2d, ], "pmovsxwd xmm3, qword fs:[rbp + 0x2da80f69]"); + test_display(&[0x2e, 0x66, 0x26, 0x64, 0x49, 0x0f, 0x3a, 0x21, 0x0b, 0xb1, ], "insertps xmm1, dword fs:[r11], -0x4f"); + test_display(&[0x66, 0x26, 0x45, 0x0f, 0x3a, 0x42, 0x96, 0x74, 0x29, 0x96, 0xf9, 0x6a], "mpsadbw xmm10, xmmword [r14 - 0x669d68c], 0x6a"); + test_display(&[0x67, 0x26, 0x66, 0x65, 0x0f, 0x38, 0x3f, 0x9d, 0xcc, 0x03, 0xb3, 0xfa], "pmaxud xmm3, xmmword gs:[ebp - 0x54cfc34]"); + test_display(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e, ], "movdiri dword [rbp + 0x3e], edx"); + test_display(&[0x36, 0x26, 0x66, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b rbp, zmmword [rbp + 0x729080b]"); test_invalid(&[0x66, 0x2e, 0x64, 0x66, 0x46, 0x0f, 0x38, 0xf8, 0xe2]); - test_display(&[0x36, 0x26, 0x66, 0x67, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b ebp, [ebp + 0x729080b]"); + test_display(&[0x36, 0x26, 0x66, 0x67, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b ebp, zmmword [ebp + 0x729080b]"); test_display(&[0x67, 0x66, 0x65, 0x3e, 0x0f, 0x6d, 0xd1], "punpckhqdq xmm2, xmm1"); - test_display(&[0x2e, 0x66, 0x40, 0x0f, 0x3a, 0x0d, 0x40, 0x2d, 0x57], "blendpd xmm0, [rax + 0x2d], 0x57"); - test_display(&[0xf2, 0x3e, 0x26, 0x67, 0x0f, 0xf0, 0xa0, 0x1b, 0x5f, 0xcd, 0xd7], "lddqu xmm4, [eax - 0x2832a0e5]"); - test_display(&[0x2e, 0x3e, 0x66, 0x3e, 0x49, 0x0f, 0x3a, 0x41, 0x30, 0x48], "dppd xmm6, [r8], 0x48"); + test_display(&[0x2e, 0x66, 0x40, 0x0f, 0x3a, 0x0d, 0x40, 0x2d, 0x57], "blendpd xmm0, xmmword [rax + 0x2d], 0x57"); + test_display(&[0xf2, 0x3e, 0x26, 0x67, 0x0f, 0xf0, 0xa0, 0x1b, 0x5f, 0xcd, 0xd7], "lddqu xmm4, xmmword [eax - 0x2832a0e5]"); + test_display(&[0x2e, 0x3e, 0x66, 0x3e, 0x49, 0x0f, 0x3a, 0x41, 0x30, 0x48], "dppd xmm6, xmmword [r8], 0x48"); test_display(&[0x2e, 0x36, 0x47, 0x0f, 0x18, 0xe7], "nop r15d"); - test_display(&[0x65, 0xf0, 0x87, 0x0f], "lock xchg gs:[rdi], ecx"); - test_display(&[0x66, 0x4e, 0x0f, 0x3a, 0x44, 0x88, 0xb3, 0xad, 0x26, 0x35, 0x75], "pclmulqdq xmm9, [rax + 0x3526adb3], 0x75"); - test_display(&[0x4c, 0x0f, 0xff, 0x6b, 0xac], "ud0 r13d, [rbx - 0x54]"); + test_display(&[0x65, 0xf0, 0x87, 0x0f], "lock xchg dword gs:[rdi], ecx"); + test_display(&[0x66, 0x4e, 0x0f, 0x3a, 0x44, 0x88, 0xb3, 0xad, 0x26, 0x35, 0x75], "pclmulqdq xmm9, xmmword [rax + 0x3526adb3], 0x75"); + test_display(&[0x4c, 0x0f, 0xff, 0x6b, 0xac], "ud0 r13d, dword [rbx - 0x54]"); - test_display(&[0xf2, 0xf2, 0x2e, 0x36, 0x47, 0x0f, 0x38, 0xf8, 0x83, 0x09, 0x1c, 0x9d, 0x3f], "enqcmd r8d, [r11 + 0x3f9d1c09]"); - test_display(&[0x3e, 0x64, 0xf3, 0x64, 0x0f, 0x38, 0xf8, 0x72, 0x54], "enqcmds esi, fs:[rdx + 0x54]"); + test_display(&[0xf2, 0xf2, 0x2e, 0x36, 0x47, 0x0f, 0x38, 0xf8, 0x83, 0x09, 0x1c, 0x9d, 0x3f], "enqcmd r8, zmmword [r11 + 0x3f9d1c09]"); + test_display(&[0x3e, 0x64, 0xf3, 0x64, 0x0f, 0x38, 0xf8, 0x72, 0x54], "enqcmds rsi, zmmword fs:[rdx + 0x54]"); test_invalid(&[0xf3, 0x0f, 0x38, 0xf8, 0xf3]); test_display(&[0xf3, 0x64, 0x2e, 0x65, 0x0f, 0x38, 0xdc, 0xe8], "loadiwkey xmm5, xmm0"); @@ -3387,8 +3205,8 @@ fn test_cet() { // endbr32 f3 0f ae fb test_display(&[0xf3, 0x4f, 0x0f, 0xae, 0xe9], "incssp r9"); test_display(&[0xf3, 0x0f, 0xae, 0xe9], "incssp ecx"); - test_display(&[0x3e, 0x4f, 0x0f, 0x38, 0xf6, 0x23], "wrss [r11], r12"); - test_display(&[0x66, 0x0f, 0x38, 0xf5, 0x47, 0xe9], "wruss [rdi - 0x17], eax"); + test_display(&[0x3e, 0x4f, 0x0f, 0x38, 0xf6, 0x23], "wrss qword [r11], r12"); + test_display(&[0x66, 0x0f, 0x38, 0xf5, 0x47, 0xe9], "wruss dword [rdi - 0x17], eax"); test_invalid(&[0x0f, 0x38, 0xf5, 0x47, 0xe9]); test_invalid(&[0x66, 0x3e, 0x65, 0x3e, 0x0f, 0x38, 0xf5, 0xf0]); test_display(&[0xf3, 0x0f, 0x01, 0xe8], "setssbsy"); @@ -3397,9 +3215,9 @@ fn test_cet() { test_display(&[0x66, 0xf3, 0x0f, 0x01, 0xea], "saveprevssp"); test_display(&[0xf3, 0x66, 0x0f, 0x01, 0xe8], "setssbsy"); test_display(&[0xf3, 0x66, 0x0f, 0x01, 0xea], "saveprevssp"); - test_display(&[0xf3, 0x0f, 0x01, 0x29], "rstorssp [rcx]"); - test_display(&[0xf3, 0x66, 0x0f, 0x01, 0x29], "rstorssp [rcx]"); - test_display(&[0xf3, 0x0f, 0xae, 0x30], "clrssbsy [rax]"); + test_display(&[0xf3, 0x0f, 0x01, 0x29], "rstorssp qword [rcx]"); + test_display(&[0xf3, 0x66, 0x0f, 0x01, 0x29], "rstorssp qword [rcx]"); + test_display(&[0xf3, 0x0f, 0xae, 0x30], "clrssbsy qword [rax]"); } #[test] @@ -3410,9 +3228,9 @@ fn test_sse4a() { test_invalid_under(&InstDecoder::minimal(), bytes); } - test_instr(&[0xf2, 0x0f, 0x2b, 0x06], "movntsd [rsi], xmm0"); + test_instr(&[0xf2, 0x0f, 0x2b, 0x06], "movntsd qword [rsi], xmm0"); test_invalid(&[0xf2, 0x0f, 0x2b, 0xc6]); - test_instr(&[0xf3, 0x0f, 0x2b, 0x06], "movntss [rsi], xmm0"); + test_instr(&[0xf3, 0x0f, 0x2b, 0x06], "movntss dword [rsi], xmm0"); test_invalid(&[0xf3, 0x0f, 0xba, 0xc6]); test_instr(&[0x66, 0xf2, 0x0f, 0x79, 0xcf], "insertq xmm1, xmm7"); test_invalid(&[0x66, 0xf2, 0x0f, 0x79, 0x0f]); @@ -3428,10 +3246,10 @@ fn test_sse4a() { #[test] fn test_3dnow() { test_display(&[0x0f, 0x0f, 0xe0, 0x8a], "pfnacc mm4, mm0"); - test_display(&[0x0f, 0x0f, 0x38, 0x8e], "pfpnacc mm7, [rax]"); + test_display(&[0x0f, 0x0f, 0x38, 0x8e], "pfpnacc mm7, qword [rax]"); test_display(&[0x65, 0x67, 0x65, 0x65, 0x0f, 0x0e], "femms"); - test_display(&[0x3e, 0xf3, 0x2e, 0xf2, 0x0f, 0x0f, 0x64, 0x93, 0x93, 0xa4], "pfmax mm4, [rbx + rdx * 4 - 0x6d]"); - test_display(&[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], "pi2fw mm6, [rax - 0x5]"); + test_display(&[0x3e, 0xf3, 0x2e, 0xf2, 0x0f, 0x0f, 0x64, 0x93, 0x93, 0xa4], "pfmax mm4, qword [rbx + rdx * 4 - 0x6d]"); + test_display(&[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], "pi2fw mm6, qword [rax - 0x5]"); test_display(&[0x66, 0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); test_display(&[0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); } @@ -3439,9 +3257,9 @@ fn test_3dnow() { // first appeared in tremont #[test] fn test_direct_stores() { - test_display(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e, ], "movdiri [rbp + 0x3e], edx"); - test_display(&[0x36, 0x26, 0x66, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b rbp, [rbp + 0x729080b]"); - test_display(&[0x36, 0x26, 0x66, 0x67, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b ebp, [ebp + 0x729080b]"); + test_display(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e, ], "movdiri dword [rbp + 0x3e], edx"); + test_display(&[0x36, 0x26, 0x66, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b rbp, zmmword [rbp + 0x729080b]"); + test_display(&[0x36, 0x26, 0x66, 0x67, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b ebp, zmmword [ebp + 0x729080b]"); } #[test] @@ -3468,15 +3286,15 @@ fn test_uintr() { // started shipping in sapphire rapids #[test] fn test_enqcmd() { - test_display(&[0xf2, 0xf2, 0x2e, 0x36, 0x47, 0x0f, 0x38, 0xf8, 0x83, 0x09, 0x1c, 0x9d, 0x3f], "enqcmd r8d, [r11 + 0x3f9d1c09]"); - test_display(&[0x3e, 0x64, 0xf3, 0x64, 0x0f, 0x38, 0xf8, 0x72, 0x54], "enqcmds esi, fs:[rdx + 0x54]"); + test_display(&[0xf2, 0xf2, 0x2e, 0x36, 0x47, 0x0f, 0x38, 0xf8, 0x83, 0x09, 0x1c, 0x9d, 0x3f], "enqcmd r8, zmmword [r11 + 0x3f9d1c09]"); + test_display(&[0x3e, 0x64, 0xf3, 0x64, 0x0f, 0x38, 0xf8, 0x72, 0x54], "enqcmds rsi, zmmword fs:[rdx + 0x54]"); } #[test] fn test_gfni() { - test_display(&[0x3e, 0x64, 0x64, 0x66, 0x4e, 0x0f, 0x3a, 0xcf, 0xba, 0x13, 0x23, 0x04, 0xba, 0x6b], "gf2p8affineinvqb xmm15, fs:[rdx - 0x45fbdced], 0x6b"); - test_display(&[0x66, 0x36, 0x0f, 0x3a, 0xce, 0x8c, 0x56, 0x9e, 0x82, 0xd1, 0xbe, 0xad], "gf2p8affineqb xmm1, [rsi + rdx * 2 - 0x412e7d62], 0xad"); - test_display(&[0x66, 0x4e, 0x0f, 0x38, 0xcf, 0x1c, 0x54], "gf2p8mulb xmm11, [rsp + r10 * 2]"); + test_display(&[0x3e, 0x64, 0x64, 0x66, 0x4e, 0x0f, 0x3a, 0xcf, 0xba, 0x13, 0x23, 0x04, 0xba, 0x6b], "gf2p8affineinvqb xmm15, xmmword fs:[rdx - 0x45fbdced], 0x6b"); + test_display(&[0x66, 0x36, 0x0f, 0x3a, 0xce, 0x8c, 0x56, 0x9e, 0x82, 0xd1, 0xbe, 0xad], "gf2p8affineqb xmm1, xmmword [rsi + rdx * 2 - 0x412e7d62], 0xad"); + test_display(&[0x66, 0x4e, 0x0f, 0x38, 0xcf, 0x1c, 0x54], "gf2p8mulb xmm11, xmmword [rsp + r10 * 2]"); } #[test] |