aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--src/long_mode/display.rs2
-rw-r--r--src/long_mode/evex.rs2
-rw-r--r--src/long_mode/vex.rs107
-rw-r--r--test/long_mode/evex_generated.rs3
4 files changed, 12 insertions, 102 deletions
diff --git a/src/long_mode/display.rs b/src/long_mode/display.rs
index 0af8bfc..4702861 100644
--- a/src/long_mode/display.rs
+++ b/src/long_mode/display.rs
@@ -5,7 +5,7 @@ use core::fmt;
use yaxpeax_arch::{Colorize, ShowContextual, NoColors, YaxColors};
use yaxpeax_arch::display::*;
-use crate::long_mode::{RegSpec, Opcode, Operand, MergeMode, InstDecoder, Instruction, SaeMode, Segment, PrefixRex, OperandSpec};
+use crate::long_mode::{RegSpec, Opcode, Operand, MergeMode, InstDecoder, Instruction, Segment, PrefixRex, OperandSpec};
impl fmt::Display for InstDecoder {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
diff --git a/src/long_mode/evex.rs b/src/long_mode/evex.rs
index 88f0494..da90d29 100644
--- a/src/long_mode/evex.rs
+++ b/src/long_mode/evex.rs
@@ -1,6 +1,6 @@
// use crate::long_mode::{OperandSpec, DecodeError, RegSpec, RegisterBank, Instruction, Opcode};
use crate::long_mode::{DecodeError, RegSpec, RegisterBank, Instruction, Opcode};
-use crate::long_mode::{read_modrm, read_E, read_E_xmm, read_E_ymm, read_E_zmm, read_imm_unsigned};
+use crate::long_mode::{read_modrm, read_E_xmm, read_E_ymm, read_E_zmm, read_imm_unsigned};
include!("../shared/generated_evex.in");
include!("../shared/evex.in");
diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs
index d7e2257..7a58fe6 100644
--- a/src/long_mode/vex.rs
+++ b/src/long_mode/vex.rs
@@ -42,7 +42,6 @@ enum VEXOperandCode {
VMOVLPS_12,
VMOVHPS_16,
E_G_xmm,
- U_G_xmm,
M_G_xmm,
G_M_xmm,
G_U_xmm,
@@ -52,16 +51,11 @@ enum VEXOperandCode {
Ud_G_xmm,
Ud_G_ymm,
E_G_ymm,
- U_G_ymm,
M_G_ymm,
G_E_ymm,
G_M_ymm,
- G_U_ymm,
Gd_U_ymm,
- E_V_G_ymm,
- E_V_G_xmm,
E_xmm_G_ymm_imm8,
- Ev_G_xmm_imm8,
Eb_G_xmm_imm8,
Ew_G_xmm_imm8,
Ed_G_xmm_imm8,
@@ -92,7 +86,6 @@ enum VEXOperandCode {
G_V_xmm_Eq_imm8,
G_V_M_xmm,
G_V_M_ymm,
- V_xmm_G_ymm_E_ymm_imm8,
G_ymm_V_ymm_E_xmm_imm8,
G_V_xmm_Ew_imm8,
Eq_G_xmm,
@@ -103,8 +96,6 @@ enum VEXOperandCode {
G_V_E,
G_E_Ib,
VCVT_Gd_Ed_xmm,
- VCVT_Gd_Eq_xmm,
- VCVT_Gq_Ed_xmm,
VCVT_Gq_Eq_xmm,
BMI1_F3,
MXCSR,
@@ -559,22 +550,6 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
instruction.operand_count = 4;
Ok(())
}
- VEXOperandCode::Ev_G_xmm_imm8 => {
- if instruction.vex_reg.num != 0 {
- instruction.opcode = Opcode::Invalid;
- return Err(DecodeError::InvalidOperand);
- }
- let modrm = read_modrm(bytes, length)?;
- instruction.modrm_rrr =
- RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
- let mem_oper = read_E(bytes, instruction, modrm, 8, length)?;
- instruction.operands[0] = mem_oper;
- instruction.operands[1] = OperandSpec::RegRRR;
- instruction.operands[2] = OperandSpec::ImmU8;
- instruction.operand_count = 3;
- instruction.imm = read_imm_unsigned(bytes, 1, length)?;
- Ok(())
- },
VEXOperandCode::G_xmm_Eq => {
if instruction.vex_reg.num != 0 {
instruction.opcode = Opcode::Invalid;
@@ -650,44 +625,6 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
instruction.operand_count = 2;
Ok(())
}
- VEXOperandCode::VCVT_Gd_Eq_xmm => {
- if instruction.vex_reg.num != 0 {
- instruction.opcode = Opcode::Invalid;
- return Err(DecodeError::InvalidOperand);
- }
- let modrm = read_modrm(bytes, length)?;
- instruction.modrm_rrr =
- RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::D);
- let mem_oper = read_E(bytes, instruction, modrm, 4, length)?;
- if let OperandSpec::RegMMM = mem_oper {
- instruction.modrm_mmm.bank = RegisterBank::X;
- } else {
- instruction.mem_size = 8;
- }
- instruction.operands[0] = OperandSpec::RegRRR;
- instruction.operands[1] = mem_oper;
- instruction.operand_count = 2;
- Ok(())
- }
- VEXOperandCode::VCVT_Gq_Ed_xmm => {
- if instruction.vex_reg.num != 0 {
- instruction.opcode = Opcode::Invalid;
- return Err(DecodeError::InvalidOperand);
- }
- let modrm = read_modrm(bytes, length)?;
- instruction.modrm_rrr =
- RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Q);
- let mem_oper = read_E(bytes, instruction, modrm, 4, length)?;
- if let OperandSpec::RegMMM = mem_oper {
- instruction.modrm_mmm.bank = RegisterBank::X;
- } else {
- instruction.mem_size = 4;
- }
- instruction.operands[0] = OperandSpec::RegRRR;
- instruction.operands[1] = mem_oper;
- instruction.operand_count = 2;
- Ok(())
- }
VEXOperandCode::VCVT_Gq_Eq_xmm => {
if instruction.vex_reg.num != 0 {
instruction.opcode = Opcode::Invalid;
@@ -708,7 +645,6 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
Ok(())
}
op @ VEXOperandCode::E_G_xmm |
- op @ VEXOperandCode::U_G_xmm |
op @ VEXOperandCode::M_G_xmm => {
if instruction.vex_reg.num != 0 {
instruction.opcode = Opcode::Invalid;
@@ -722,7 +658,6 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
(VEXOperandCode::E_G_xmm, OperandSpec::RegMMM) => {
/* this is the only accepted operand */
}
- (VEXOperandCode::U_G_xmm, _) |
(VEXOperandCode::M_G_xmm, OperandSpec::RegMMM) => {
return Err(DecodeError::InvalidOperand);
}
@@ -950,7 +885,6 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
}
op @ VEXOperandCode::E_G_ymm |
- op @ VEXOperandCode::U_G_ymm |
op @ VEXOperandCode::M_G_ymm => {
if instruction.vex_reg.num != 0 {
instruction.opcode = Opcode::Invalid;
@@ -958,10 +892,6 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
}
let modrm = read_modrm(bytes, length)?;
match (op, modrm & 0xc0) {
- (VEXOperandCode::U_G_ymm, 0xc0) => {
- /* this is the only accepted operand */
- }
- (VEXOperandCode::U_G_ymm, _) |
(VEXOperandCode::M_G_ymm, 0xc0) => {
return Err(DecodeError::InvalidOperand);
}
@@ -980,7 +910,6 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
}
op @ VEXOperandCode::G_M_ymm |
- op @ VEXOperandCode::G_U_ymm |
op @ VEXOperandCode::G_E_ymm => {
if instruction.vex_reg.num != 0 {
instruction.opcode = Opcode::Invalid;
@@ -988,10 +917,6 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
}
let modrm = read_modrm(bytes, length)?;
match (op, modrm & 0xc0) {
- (VEXOperandCode::G_U_ymm, 0xc0) => {
- /* this is the only accepted operand */
- }
- (VEXOperandCode::G_U_ymm, _) |
(VEXOperandCode::G_M_ymm, 0xc0) => {
return Err(DecodeError::InvalidOperand);
}
@@ -1040,13 +965,10 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
instruction.operand_count = 4;
Ok(())
}
- op @ VEXOperandCode::E_V_G_ymm |
- op @ VEXOperandCode::M_V_G_ymm => {
+ VEXOperandCode::M_V_G_ymm => {
let modrm = read_modrm(bytes, length)?;
- if let VEXOperandCode::M_V_G_ymm = op {
- if modrm & 0xc0 == 0xc0 {
- return Err(DecodeError::InvalidOperand);
- }
+ if modrm & 0xc0 == 0xc0 {
+ return Err(DecodeError::InvalidOperand);
}
instruction.modrm_rrr =
RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
@@ -1136,27 +1058,12 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst
instruction.operand_count = 4;
Ok(())
}
- _op @ VEXOperandCode::V_xmm_G_ymm_E_ymm_imm8 => {
+ VEXOperandCode::M_V_G_xmm => {
let modrm = read_modrm(bytes, length)?;
- instruction.modrm_rrr =
- RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::Y);
- let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?;
- instruction.operands[0] = OperandSpec::RegVex;
- instruction.operands[1] = OperandSpec::RegRRR;
- instruction.operands[2] = mem_oper;
- instruction.imm = read_imm_unsigned(bytes, 1, length)?;
- instruction.operands[3] = OperandSpec::ImmU8;
- instruction.operand_count = 4;
- Ok(())
- }
- op @ VEXOperandCode::E_V_G_xmm |
- op @ VEXOperandCode::M_V_G_xmm => {
- let modrm = read_modrm(bytes, length)?;
- if let VEXOperandCode::M_V_G_xmm = op {
- if modrm & 0xc0 == 0xc0 {
- return Err(DecodeError::InvalidOperand);
- }
+ if modrm & 0xc0 == 0xc0 {
+ return Err(DecodeError::InvalidOperand);
}
+
instruction.modrm_rrr =
RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex().r(), RegisterBank::X);
let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?;
diff --git a/test/long_mode/evex_generated.rs b/test/long_mode/evex_generated.rs
index c948c0e..9c23e4b 100644
--- a/test/long_mode/evex_generated.rs
+++ b/test/long_mode/evex_generated.rs
@@ -3,6 +3,7 @@ use std::fmt::Write;
use yaxpeax_arch::{AddressBase, Decoder, LengthedInstruction};
use yaxpeax_x86::long_mode::InstDecoder;
+#[allow(dead_code)]
fn test_invalid(data: &[u8]) {
test_invalid_under(&InstDecoder::default(), data);
}
@@ -15,6 +16,7 @@ fn test_invalid_under(decoder: &InstDecoder, data: &[u8]) {
}
}
+#[allow(dead_code)]
fn test_display(data: &[u8], expected: &'static str) {
test_display_under(&InstDecoder::default(), data, expected);
}
@@ -54,6 +56,7 @@ fn test_avx_full(bytes: &[u8], text: &'static str) {
test_invalid_under(&InstDecoder::minimal(), bytes);
}
+#[allow(non_snake_case)]
#[test]
fn tests_None_0f() {
test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x10, 0xca], "vmovups ymm1{k5}{z}, ymm2"); // VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX
generated by cgit v1.1 at 2024-11-01 03:28:45 +0000