diff options
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 14 |
1 files changed, 8 insertions, 6 deletions
@@ -15,12 +15,14 @@ access size, fixing the prior behavior of reporting no memory access size at all * table load/store instructions (lgdt, lidt, lldt, sgdt, sidt, sldt) have correct (mode-dependent) memory access sizes, rather than incorrectly varying on operand-size overrides. -* 64-bit mode: mov seg-to-reg uses 32-bit GPRs for the destination rather than 16-bit. - * this is more accurate to the semantic of the instruction, which is why other disassemblers - report it this way; for register destinations specifically the segment selector is - zero-extended to 64 bits for storage. writing to "eax" in this way implies the 32->64 bit - zero-extend, whereas writing to "ax" does not imply any zero-extension. mov reg-to-seg - is unchanged and uses a 16-bit form for source GPR. +* mov seg-to-reg has more careful destination GPR selection. + * 64-bit: use 32-bit GPRs for the destination rather than 16-bit. + - this is more accurate to the semantic of the instruction, which is why other disassemblers + report it this way; for register destinations specifically the segment selector is + zero-extended to 64 bits for storage. writing to "eax" in this way implies the 32->64 bit + zero-extend, whereas writing to "ax" does not imply any zero-extension. mov reg-to-seg + is unchanged and uses a 16-bit form for source GPR. + * 32-bit, 16-bit: use 32-bit or 16-bit GPRs as requested by mode and operand size prefixes. * fix pextr{b,w,d,q} and extractps first and second operands being backwards. * reject 0f0d prefetch/nop with a register operand, which was incorrectly decoded before. * maskmovq and maskmovdqu now have their implicit memory access size reported correctly. |