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-rw-r--r--src/long_mode/mod.rs7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 5c431b4..3fcf4ab 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -368,6 +368,7 @@ impl OperandSpec {
OperandSpec::RegRRR |
OperandSpec::RegMMM |
OperandSpec::RegVex |
+ OperandSpec::Reg4 |
OperandSpec::EnterFrameSize |
OperandSpec::Nothing => {
false
@@ -392,6 +393,9 @@ impl Operand {
OperandSpec::RegVex => {
Operand::Register(inst.vex_reg)
}
+ OperandSpec::Reg4 => {
+ Operand::Register(RegSpec { num: inst.imm as u8, bank: inst.vex_reg.bank })
+ }
OperandSpec::ImmI8 => Operand::ImmediateI8(inst.imm as i8),
OperandSpec::ImmU8 => Operand::ImmediateU8(inst.imm as u8),
OperandSpec::ImmI16 => Operand::ImmediateI16(inst.imm as i16),
@@ -1596,6 +1600,9 @@ enum OperandSpec {
RegMMM,
// the register selected by vex-vvvv bits
RegVex,
+ // the register selected by a handful of avx2 vex-coded instructions,
+ // stuffed in imm4.
+ Reg4,
ImmI8,
ImmI16,
ImmI32,