diff options
Diffstat (limited to 'src/long_mode')
| -rw-r--r-- | src/long_mode/uarch.rs | 2 | ||||
| -rw-r--r-- | src/long_mode/vex.rs | 12 |
2 files changed, 10 insertions, 4 deletions
diff --git a/src/long_mode/uarch.rs b/src/long_mode/uarch.rs index 63fa972..9cfc9de 100644 --- a/src/long_mode/uarch.rs +++ b/src/long_mode/uarch.rs @@ -145,6 +145,7 @@ pub mod amd { .with_rdrand() .with_rdseed() .with_fma3() + .with_f16c() .with_xsavec() .with_xsaves() @@ -272,6 +273,7 @@ pub mod intel { .with_abm() .with_fma3() .with_avx2() + .with_f16c() } /// `Haswell-EX` was a variant of `Haswell` launched in 2015 with functional TSX. these cores diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs index 1d94b3c..a847fc0 100644 --- a/src/long_mode/vex.rs +++ b/src/long_mode/vex.rs @@ -2755,11 +2755,15 @@ fn read_vex_instruction< return Err(DecodeError::InvalidOpcode); }) }, - 0x1D => (Opcode::VCVTPS2PH, if L { - VEXOperandCode::E_xmm_G_ymm_imm8 + 0x1D => if instruction.prefixes.vex_unchecked().w() { + return Err(DecodeError::InvalidOpcode); } else { - VEXOperandCode::E_G_xmm_imm8 - }), + (Opcode::VCVTPS2PH, if L { + VEXOperandCode::E_xmm_G_ymm_imm8 + } else { + VEXOperandCode::E_G_xmm_imm8 + }) + }, 0x20 => (Opcode::VPINSRB, if L { return Err(DecodeError::InvalidOpcode); } else { |