diff options
Diffstat (limited to 'src/long_mode')
| -rw-r--r-- | src/long_mode/mod.rs | 7 | ||||
| -rw-r--r-- | src/long_mode/vex.rs | 28 |
2 files changed, 35 insertions, 0 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 5c431b4..3fcf4ab 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -368,6 +368,7 @@ impl OperandSpec { OperandSpec::RegRRR | OperandSpec::RegMMM | OperandSpec::RegVex | + OperandSpec::Reg4 | OperandSpec::EnterFrameSize | OperandSpec::Nothing => { false @@ -392,6 +393,9 @@ impl Operand { OperandSpec::RegVex => { Operand::Register(inst.vex_reg) } + OperandSpec::Reg4 => { + Operand::Register(RegSpec { num: inst.imm as u8, bank: inst.vex_reg.bank }) + } OperandSpec::ImmI8 => Operand::ImmediateI8(inst.imm as i8), OperandSpec::ImmU8 => Operand::ImmediateU8(inst.imm as u8), OperandSpec::ImmI16 => Operand::ImmediateI16(inst.imm as i16), @@ -1596,6 +1600,9 @@ enum OperandSpec { RegMMM, // the register selected by vex-vvvv bits RegVex, + // the register selected by a handful of avx2 vex-coded instructions, + // stuffed in imm4. + Reg4, ImmI8, ImmI16, ImmI32, diff --git a/src/long_mode/vex.rs b/src/long_mode/vex.rs index 8563fc7..7c4e27d 100644 --- a/src/long_mode/vex.rs +++ b/src/long_mode/vex.rs @@ -798,6 +798,34 @@ fn read_vex_operands<T: Iterator<Item=u8>>(bytes: &mut T, instruction: &mut Inst instruction.operand_count = 3; Ok(()) } + VEXOperandCode::G_V_E_ymm_ymm4 => { + let modrm = read_modrm(bytes, length)?; + instruction.modrm_rrr = + RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), RegisterBank::Y); + instruction.vex_reg.bank = RegisterBank::Y; + let mem_oper = read_E_ymm(bytes, instruction, modrm, length)?; + instruction.operands[0] = OperandSpec::RegRRR; + instruction.operands[1] = OperandSpec::RegVex; + instruction.operands[2] = mem_oper; + instruction.imm = read_imm_unsigned(bytes, 1, length)? >> 4; + instruction.operands[3] = OperandSpec::Reg4; + instruction.operand_count = 4; + Ok(()) + } + VEXOperandCode::G_V_E_xmm_xmm4 => { + let modrm = read_modrm(bytes, length)?; + instruction.modrm_rrr = + RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex().x(), RegisterBank::X); + instruction.vex_reg.bank = RegisterBank::X; + let mem_oper = read_E_xmm(bytes, instruction, modrm, length)?; + instruction.operands[0] = OperandSpec::RegRRR; + instruction.operands[1] = OperandSpec::RegVex; + instruction.operands[2] = mem_oper; + instruction.imm = read_imm_unsigned(bytes, 1, length)? >> 4; + instruction.operands[3] = OperandSpec::Reg4; + instruction.operand_count = 4; + Ok(()) + } VEXOperandCode::G_V_E_xmm_xmm4 | VEXOperandCode::G_V_E_ymm_ymm4 | |