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-rw-r--r--src/protected_mode/mod.rs15
1 files changed, 8 insertions, 7 deletions
diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs
index 8ac87be..42595a8 100644
--- a/src/protected_mode/mod.rs
+++ b/src/protected_mode/mod.rs
@@ -112,32 +112,32 @@ impl RegSpec {
#[inline]
pub fn cs() -> RegSpec {
- RegSpec { bank: RegisterBank::S, num: 0 }
+ RegSpec { bank: RegisterBank::S, num: 1 }
}
#[inline]
pub fn ds() -> RegSpec {
- RegSpec { bank: RegisterBank::S, num: 1 }
+ RegSpec { bank: RegisterBank::S, num: 3 }
}
#[inline]
pub fn es() -> RegSpec {
- RegSpec { bank: RegisterBank::S, num: 2 }
+ RegSpec { bank: RegisterBank::S, num: 0 }
}
#[inline]
pub fn ss() -> RegSpec {
- RegSpec { bank: RegisterBank::S, num: 5 }
+ RegSpec { bank: RegisterBank::S, num: 2 }
}
#[inline]
pub fn fs() -> RegSpec {
- RegSpec { bank: RegisterBank::S, num: 3 }
+ RegSpec { bank: RegisterBank::S, num: 4 }
}
#[inline]
pub fn gs() -> RegSpec {
- RegSpec { bank: RegisterBank::S, num: 4 }
+ RegSpec { bank: RegisterBank::S, num: 5 }
}
#[inline]
@@ -1407,6 +1407,7 @@ pub enum Opcode {
WRGSBASE,
CRC32,
+ SALC,
XLAT,
F2XM1,
@@ -5149,7 +5150,7 @@ const OPCODES: [OpcodeRecord; 256] = [
OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd3_Ev_CL),
OpcodeRecord(Interpretation::Instruction(Opcode::AMX), OperandCode::Ib),
OpcodeRecord(Interpretation::Instruction(Opcode::ADX), OperandCode::Ib),
- OpcodeRecord(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing),
+ OpcodeRecord(Interpretation::Instruction(Opcode::SALC), OperandCode::Nothing),
// XLAT
OpcodeRecord(Interpretation::Instruction(Opcode::XLAT), OperandCode::Nothing),
// x86 d8