diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/long_mode/display.rs | 2 | ||||
| -rw-r--r-- | src/long_mode/mod.rs | 26 |
2 files changed, 28 insertions, 0 deletions
diff --git a/src/long_mode/display.rs b/src/long_mode/display.rs index d45a98a..3025c16 100644 --- a/src/long_mode/display.rs +++ b/src/long_mode/display.rs @@ -652,6 +652,7 @@ impl fmt::Display for Opcode { &Opcode::BLSMSK => write!(f, "blsmsk"), &Opcode::BLSR => write!(f, "blsr"), &Opcode::VMCLEAR => write!(f, "vmclear"), + &Opcode::VMXON => write!(f, "vmxon"), &Opcode::VMCALL => write!(f, "vmcall"), &Opcode::VMLAUNCH => write!(f, "vmlaunch"), &Opcode::VMRESUME => write!(f, "vmresume"), @@ -1855,6 +1856,7 @@ impl <T: fmt::Write, Color: fmt::Display, Y: YaxColors<Color>> Colorize<T, Color Opcode::VMREAD | Opcode::VMWRITE | Opcode::VMCLEAR | + Opcode::VMXON | Opcode::VMCALL | Opcode::VMLAUNCH | Opcode::VMRESUME | diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs index 79e5b39..73570c1 100644 --- a/src/long_mode/mod.rs +++ b/src/long_mode/mod.rs @@ -659,6 +659,7 @@ pub enum Opcode { BLSMSK, BLSR, VMCLEAR, + VMXON, VMCALL, VMLAUNCH, VMRESUME, @@ -5111,6 +5112,13 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T, Opcode::PUSH, Opcode::Invalid ][((modrm >> 3) & 7) as usize]; + if instruction.operands[0] == OperandSpec::RegMMM { + if opcode == Opcode::CALL || opcode == Opcode::JMP { + instruction.modrm_mmm.bank = RegisterBank::Q; + } else if opcode == Opcode::CALLF || opcode == Opcode::JMPF { + return Err(DecodeError::InvalidOperand); + } + } instruction.opcode = opcode; instruction.operand_count = 1; } @@ -5643,6 +5651,24 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter } } }, + OperandCode::ModRM_0xf30fc7 => { + let modrm = read_modrm(&mut bytes_iter, length)?; + + let r = (modrm >> 3) & 7; + match r { + 6 => { + instruction.opcode = Opcode::VMXON; + instruction.operands[0] = read_E(&mut bytes_iter, instruction, modrm, 1 /* doesn't matter, something using this width is invalid */, length)?; + if instruction.operands[0] == OperandSpec::RegMMM { + return Err(DecodeError::InvalidOperand); + } + instruction.operand_count = 1; + } + _ => { + return Err(DecodeError::InvalidOpcode); + } + } + }, OperandCode::G_mm_Edq => { instruction.operands[1] = mem_oper; instruction.modrm_rrr.bank = RegisterBank::MM; |