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-rw-r--r--src/lib.rs550
1 files changed, 124 insertions, 426 deletions
diff --git a/src/lib.rs b/src/lib.rs
index 34c4470..6b571a2 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -774,86 +774,32 @@ fn read_opcode_f20f_map<T: Iterator<Item=u8>>(bytes_iter: &mut T, instruction: &
match bytes_iter.next() {
Some(b) => {
*length += 1;
- match b {
- 0x10 => {
- instruction.opcode = Opcode::MOVSD;
- Ok(OperandCode::G_E_xmm)
- },
- 0x11 => {
- instruction.opcode = Opcode::MOVSD;
- Ok(OperandCode::E_G_xmm)
- },
- 0x12 => {
- instruction.opcode = Opcode::MOVDDUP;
- Ok(OperandCode::G_E_xmm)
- },
- 0x2a => {
- instruction.opcode = Opcode::CVTSI2SD;
- Ok(OperandCode::G_E_xmm)
- },
- 0x2c => {
- instruction.opcode = Opcode::CVTTSD2SI;
- Ok(OperandCode::G_E_xmm)
- },
- 0x2d => {
- instruction.opcode = Opcode::CVTSD2SI;
- Ok(OperandCode::G_E_xmm)
- },
+ let (opcode, operand_code) = match b {
+ 0x10 => { (Opcode::MOVSD, OperandCode::G_E_xmm) },
+ 0x11 => { (Opcode::MOVSD, OperandCode::E_G_xmm) },
+ 0x12 => { (Opcode::MOVDDUP, OperandCode::G_E_xmm) },
+ 0x2a => { (Opcode::CVTSI2SD, OperandCode::G_E_xmm) },
+ 0x2c => { (Opcode::CVTTSD2SI, OperandCode::G_E_xmm) },
+ 0x2d => { (Opcode::CVTSD2SI, OperandCode::G_E_xmm) },
0x38 => {
/*
* There are a handful of instruction variants here, but
* in the f20f opcode map, only the CRC32 instruction is valid
*/
- Err("x86_64 CRC32 not currently supported".to_string())
- }
- 0x51 => {
- instruction.opcode = Opcode::SQRTSD;
- Ok(OperandCode::G_E_xmm)
- },
- 0x58 => {
- instruction.opcode = Opcode::ADDSD;
- Ok(OperandCode::G_E_xmm)
- },
- 0x59 => {
- instruction.opcode = Opcode::MULSD;
- Ok(OperandCode::G_E_xmm)
- },
- 0x5a => {
- instruction.opcode = Opcode::CVTSD2SS;
- Ok(OperandCode::G_E_xmm)
- },
- 0x5c => {
- instruction.opcode = Opcode::SUBSD;
- Ok(OperandCode::G_E_xmm)
- },
- 0x5d => {
- instruction.opcode = Opcode::MINSD;
- Ok(OperandCode::G_E_xmm)
- },
- 0x5e => {
- instruction.opcode = Opcode::DIVSD;
- Ok(OperandCode::G_E_xmm)
- },
- 0x5f => {
- instruction.opcode = Opcode::MAXSD;
- Ok(OperandCode::G_E_xmm)
- },
- 0x7c => {
- instruction.opcode = Opcode::HADDPS;
- Ok(OperandCode::G_E_xmm)
- },
- 0x7d => {
- instruction.opcode = Opcode::HSUBPS;
- Ok(OperandCode::G_E_xmm)
- },
- 0xD0 => {
- instruction.opcode = Opcode::ADDSUBPS;
- Ok(OperandCode::G_E_xmm)
- },
- 0xf0 => {
- instruction.opcode = Opcode::LDDQU;
- Ok(OperandCode::G_E_xmm)
- },
+ return Err("x86_64 CRC32 not currently supported".to_string())
+ }
+ 0x51 => { (Opcode::SQRTSD, OperandCode::G_E_xmm) },
+ 0x58 => { (Opcode::ADDSD, OperandCode::G_E_xmm) },
+ 0x59 => { (Opcode::MULSD, OperandCode::G_E_xmm) },
+ 0x5a => { (Opcode::CVTSD2SS, OperandCode::G_E_xmm) },
+ 0x5c => { (Opcode::SUBSD, OperandCode::G_E_xmm) },
+ 0x5d => { (Opcode::MINSD, OperandCode::G_E_xmm) },
+ 0x5e => { (Opcode::DIVSD, OperandCode::G_E_xmm) },
+ 0x5f => { (Opcode::MAXSD, OperandCode::G_E_xmm) },
+ 0x7c => { (Opcode::HADDPS, OperandCode::G_E_xmm) },
+ 0x7d => { (Opcode::HSUBPS, OperandCode::G_E_xmm) },
+ 0xD0 => { (Opcode::ADDSUBPS, OperandCode::G_E_xmm) },
+ 0xf0 => { (Opcode::LDDQU, OperandCode::G_E_xmm) },
/*
0x70 PSHUFLW
0xc2 CMPSD
@@ -862,9 +808,11 @@ fn read_opcode_f20f_map<T: Iterator<Item=u8>>(bytes_iter: &mut T, instruction: &
*/
_ => {
instruction.opcode = Opcode::Invalid;
- Err("Invalid opcode".to_string())
+ return Err("Invalid opcode".to_string())
}
- }
+ };
+ instruction.opcode = opcode;
+ Ok(operand_code)
}
None => {
Err("No more bytes".to_owned())
@@ -875,68 +823,28 @@ fn read_opcode_f30f_map<T: Iterator<Item=u8>>(bytes_iter: &mut T, instruction: &
match bytes_iter.next() {
Some(b) => {
*length += 1;
- match b {
- 0x10 => {
- instruction.opcode = Opcode::MOVSS;
- Ok(OperandCode::G_E_xmm)
- },
- 0x11 => {
- instruction.opcode = Opcode::MOVSS;
- Ok(OperandCode::E_G_xmm)
- },
- 0x12 => {
- instruction.opcode = Opcode::MOVSLDUP;
- Ok(OperandCode::G_E_xmm)
- },
- 0x2a => {
- instruction.opcode = Opcode::CVTSI2SS;
- Ok(OperandCode::G_E_xmm)
- },
- 0x2c => {
- instruction.opcode = Opcode::CVTTSS2SI;
- Ok(OperandCode::G_E_xmm)
- },
- 0x2d => {
- instruction.opcode = Opcode::CVTSS2SI;
- Ok(OperandCode::G_E_xmm)
- },
- 0x51 => {
- instruction.opcode = Opcode::SQRTSS;
- Ok(OperandCode::G_E_xmm)
- },
- 0x58 => {
- instruction.opcode = Opcode::ADDSS;
- Ok(OperandCode::G_E_xmm)
- },
- 0x59 => {
- instruction.opcode = Opcode::MULSS;
- Ok(OperandCode::G_E_xmm)
- },
- 0x5a => {
- instruction.opcode = Opcode::CVTSS2SD;
- Ok(OperandCode::G_E_xmm)
- },
- 0x5c => {
- instruction.opcode = Opcode::SUBSS;
- Ok(OperandCode::G_E_xmm)
- },
- 0x5d => {
- instruction.opcode = Opcode::MINSS;
- Ok(OperandCode::G_E_xmm)
- },
- 0x5e => {
- instruction.opcode = Opcode::DIVSS;
- Ok(OperandCode::G_E_xmm)
- },
- 0x5f => {
- instruction.opcode = Opcode::MAXSS;
- Ok(OperandCode::G_E_xmm)
- },
+ let (opcode, operand_code) = match b {
+ 0x10 => { (Opcode::MOVSS, OperandCode::G_E_xmm) },
+ 0x11 => { (Opcode::MOVSS, OperandCode::E_G_xmm) },
+ 0x12 => { (Opcode::MOVSLDUP, OperandCode::G_E_xmm) },
+ 0x2a => { (Opcode::CVTSI2SS, OperandCode::G_E_xmm) },
+ 0x2c => { (Opcode::CVTTSS2SI, OperandCode::G_E_xmm) },
+ 0x2d => { (Opcode::CVTSS2SI, OperandCode::G_E_xmm) },
+ 0x51 => { (Opcode::SQRTSS, OperandCode::G_E_xmm) },
+ 0x58 => { (Opcode::ADDSS, OperandCode::G_E_xmm) },
+ 0x59 => { (Opcode::MULSS, OperandCode::G_E_xmm) },
+ 0x5a => { (Opcode::CVTSS2SD, OperandCode::G_E_xmm) },
+ 0x5c => { (Opcode::SUBSS, OperandCode::G_E_xmm) },
+ 0x5d => { (Opcode::MINSS, OperandCode::G_E_xmm) },
+ 0x5e => { (Opcode::DIVSS, OperandCode::G_E_xmm) },
+ 0x5f => { (Opcode::MAXSS, OperandCode::G_E_xmm) },
_ => {
instruction.opcode = Opcode::Invalid;
- Err("Invalid opcode".to_string())
+ return Err("Invalid opcode".to_string());
}
- }
+ };
+ instruction.opcode = opcode;
+ Ok(operand_code)
}
None => {
Err("No more bytes".to_owned())
@@ -947,215 +855,61 @@ fn read_opcode_0f_map<T: Iterator<Item=u8>>(bytes_iter: &mut T, instruction: &mu
match bytes_iter.next() {
Some(b) => {
*length += 1;
- match b {
- 0x00 => {
- Ok(OperandCode::ModRM_0x0f00)
- }
- 0x01 => {
- Ok(OperandCode::ModRM_0x0f01)
- }
- 0x02 => {
- instruction.opcode = Opcode::LAR;
- Ok(OperandCode::Gv_M)
- }
- 0x03 => {
- instruction.opcode = Opcode::LSL;
- Ok(OperandCode::Gv_M)
- }
- 0x05 => {
- instruction.opcode = Opcode::SYSCALL;
- Ok(OperandCode::Nothing)
- }
- 0x06 => {
- instruction.opcode = Opcode::CLTS;
- Ok(OperandCode::Nothing)
- }
- 0x07 => {
- instruction.opcode = Opcode::SYSRET;
- Ok(OperandCode::Nothing)
- }
- 0x08 => {
- instruction.opcode = Opcode::INVD;
- Ok(OperandCode::Nothing)
- }
- 0x09 => {
- instruction.opcode = Opcode::WBINVD;
- Ok(OperandCode::Nothing)
- }
- 0x0b => {
- instruction.opcode = Opcode::UD2;
- Ok(OperandCode::Nothing)
- }
- 0x0d => {
- instruction.opcode = Opcode::NOP;
- Ok(OperandCode::Ev)
- }
- 0x1f => {
- instruction.opcode = Opcode::NOP;
- Ok(OperandCode::Ev)
- },
- 0x20 => {
- instruction.opcode = Opcode::MOV;
- Ok(OperandCode::Rq_Cq_0)
- },
- 0x21 => {
- instruction.opcode = Opcode::MOV;
- Ok(OperandCode::Rq_Dq_0)
- },
- 0x22 => {
- instruction.opcode = Opcode::MOV;
- Ok(OperandCode::Cq_Rq_0)
- },
- 0x23 => {
- instruction.opcode = Opcode::MOV;
- Ok(OperandCode::Dq_Rq_0)
- },
- 0x30 => {
- instruction.opcode = Opcode::WRMSR;
- Ok(OperandCode::Nothing)
- },
- 0x31 => {
- instruction.opcode = Opcode::RDTSC;
- Ok(OperandCode::Nothing)
- },
- 0x32 => {
- instruction.opcode = Opcode::RDMSR;
- Ok(OperandCode::Nothing)
- },
- 0x33 => {
- instruction.opcode = Opcode::RDPMC;
- Ok(OperandCode::Nothing)
- },
- 0x40 => {
- instruction.opcode = Opcode::CMOVO;
- Ok(OperandCode::Gv_Ev)
- },
- 0x41 => {
- instruction.opcode = Opcode::CMOVNO;
- Ok(OperandCode::Gv_Ev)
- },
- 0x42 => {
- instruction.opcode = Opcode::CMOVB;
- Ok(OperandCode::Gv_Ev)
- },
- 0x43 => {
- instruction.opcode = Opcode::CMOVNB;
- Ok(OperandCode::Gv_Ev)
- },
- 0x44 => {
- instruction.opcode = Opcode::CMOVZ;
- Ok(OperandCode::Gv_Ev)
- },
- 0x45 => {
- instruction.opcode = Opcode::CMOVNZ;
- Ok(OperandCode::Gv_Ev)
- },
- 0x46 => {
- instruction.opcode = Opcode::CMOVNA;
- Ok(OperandCode::Gv_Ev)
- },
- 0x47 => {
- instruction.opcode = Opcode::CMOVA;
- Ok(OperandCode::Gv_Ev)
- },
- 0x48 => {
- instruction.opcode = Opcode::CMOVS;
- Ok(OperandCode::Gv_Ev)
- },
- 0x49 => {
- instruction.opcode = Opcode::CMOVNS;
- Ok(OperandCode::Gv_Ev)
- },
- 0x4a => {
- instruction.opcode = Opcode::CMOVP;
- Ok(OperandCode::Gv_Ev)
- },
- 0x4b => {
- instruction.opcode = Opcode::CMOVNP;
- Ok(OperandCode::Gv_Ev)
- },
- 0x4c => {
- instruction.opcode = Opcode::CMOVL;
- Ok(OperandCode::Gv_Ev)
- },
- 0x4d => {
- instruction.opcode = Opcode::CMOVGE;
- Ok(OperandCode::Gv_Ev)
- },
- 0x4e => {
- instruction.opcode = Opcode::CMOVLE;
- Ok(OperandCode::Gv_Ev)
- },
- 0x4f => {
- instruction.opcode = Opcode::CMOVG;
- Ok(OperandCode::Gv_Ev)
- },
- 0x80 => {
- instruction.opcode = Opcode::JO;
- Ok(OperandCode::Jvds)
- },
- 0x81 => {
- instruction.opcode = Opcode::JNO;
- Ok(OperandCode::Jvds)
- },
- 0x82 => {
- instruction.opcode = Opcode::JB;
- Ok(OperandCode::Jvds)
- },
- 0x83 => {
- instruction.opcode = Opcode::JNB;
- Ok(OperandCode::Jvds)
- },
- 0x84 => {
- instruction.opcode = Opcode::JZ;
- Ok(OperandCode::Jvds)
- },
- 0x85 => {
- instruction.opcode = Opcode::JNZ;
- Ok(OperandCode::Jvds)
- },
- 0x86 => {
- instruction.opcode = Opcode::JNA;
- Ok(OperandCode::Jvds)
- },
- 0x87 => {
- instruction.opcode = Opcode::JA;
- Ok(OperandCode::Jvds)
- },
- 0x88 => {
- instruction.opcode = Opcode::JS;
- Ok(OperandCode::Jvds)
- },
- 0x89 => {
- instruction.opcode = Opcode::JNS;
- Ok(OperandCode::Jvds)
- },
- 0x8a => {
- instruction.opcode = Opcode::JP;
- Ok(OperandCode::Jvds)
- },
- 0x8b => {
- instruction.opcode = Opcode::JNP;
- Ok(OperandCode::Jvds)
- },
- 0x8c => {
- instruction.opcode = Opcode::JL;
- Ok(OperandCode::Jvds)
- },
- 0x8d => {
- instruction.opcode = Opcode::JGE;
- Ok(OperandCode::Jvds)
- },
- 0x8e => {
- instruction.opcode = Opcode::JLE;
- Ok(OperandCode::Jvds)
- },
- 0x8f => {
- instruction.opcode = Opcode::JG;
- Ok(OperandCode::Jvds)
- },
+ let (opcode, operand_code) = match b {
+ 0x00 => { (Opcode::Invalid, OperandCode::ModRM_0x0f00) },
+ 0x01 => { (Opcode::Invalid, OperandCode::ModRM_0x0f01) },
+ 0x02 => { (Opcode::LAR, OperandCode::Gv_M) },
+ 0x03 => { (Opcode::LSL, OperandCode::Gv_M) },
+ 0x05 => { (Opcode::SYSCALL, OperandCode::Nothing) },
+ 0x06 => { (Opcode::CLTS, OperandCode::Nothing) },
+ 0x07 => { (Opcode::SYSRET, OperandCode::Nothing) },
+ 0x08 => { (Opcode::INVD, OperandCode::Nothing) },
+ 0x09 => { (Opcode::WBINVD, OperandCode::Nothing) },
+ 0x0b => { (Opcode::UD2, OperandCode::Nothing) },
+ 0x0d => { (Opcode::NOP, OperandCode::Ev) },
+ 0x1f => { (Opcode::NOP, OperandCode::Ev) },
+ 0x20 => { (Opcode::MOV, OperandCode::Rq_Cq_0) },
+ 0x21 => { (Opcode::MOV, OperandCode::Rq_Dq_0) },
+ 0x22 => { (Opcode::MOV, OperandCode::Cq_Rq_0) },
+ 0x23 => { (Opcode::MOV, OperandCode::Dq_Rq_0) },
+ 0x30 => { (Opcode::WRMSR, OperandCode::Nothing) },
+ 0x31 => { (Opcode::RDTSC, OperandCode::Nothing) },
+ 0x32 => { (Opcode::RDMSR, OperandCode::Nothing) },
+ 0x33 => { (Opcode::RDPMC, OperandCode::Nothing) },
+ 0x40 => { (Opcode::CMOVO, OperandCode::Gv_Ev) },
+ 0x41 => { (Opcode::CMOVNO, OperandCode::Gv_Ev) },
+ 0x42 => { (Opcode::CMOVB, OperandCode::Gv_Ev) },
+ 0x43 => { (Opcode::CMOVNB, OperandCode::Gv_Ev) },
+ 0x44 => { (Opcode::CMOVZ, OperandCode::Gv_Ev) },
+ 0x45 => { (Opcode::CMOVNZ, OperandCode::Gv_Ev) },
+ 0x46 => { (Opcode::CMOVNA, OperandCode::Gv_Ev) },
+ 0x47 => { (Opcode::CMOVA, OperandCode::Gv_Ev) },
+ 0x48 => { (Opcode::CMOVS, OperandCode::Gv_Ev) },
+ 0x49 => { (Opcode::CMOVNS, OperandCode::Gv_Ev) },
+ 0x4a => { (Opcode::CMOVP, OperandCode::Gv_Ev) },
+ 0x4b => { (Opcode::CMOVNP, OperandCode::Gv_Ev) },
+ 0x4c => { (Opcode::CMOVL, OperandCode::Gv_Ev) },
+ 0x4d => { (Opcode::CMOVGE, OperandCode::Gv_Ev) },
+ 0x4e => { (Opcode::CMOVLE, OperandCode::Gv_Ev) },
+ 0x4f => { (Opcode::CMOVG, OperandCode::Gv_Ev) },
+ 0x80 => { (Opcode::JO, OperandCode::Jvds) },
+ 0x81 => { (Opcode::JNO, OperandCode::Jvds) },
+ 0x82 => { (Opcode::JB, OperandCode::Jvds) },
+ 0x83 => { (Opcode::JNB, OperandCode::Jvds) },
+ 0x84 => { (Opcode::JZ, OperandCode::Jvds) },
+ 0x85 => { (Opcode::JNZ, OperandCode::Jvds) },
+ 0x86 => { (Opcode::JNA, OperandCode::Jvds) },
+ 0x87 => { (Opcode::JA, OperandCode::Jvds) },
+ 0x88 => { (Opcode::JS, OperandCode::Jvds) },
+ 0x89 => { (Opcode::JNS, OperandCode::Jvds) },
+ 0x8a => { (Opcode::JP, OperandCode::Jvds) },
+ 0x8b => { (Opcode::JNP, OperandCode::Jvds) },
+ 0x8c => { (Opcode::JL, OperandCode::Jvds) },
+ 0x8d => { (Opcode::JGE, OperandCode::Jvds) },
+ 0x8e => { (Opcode::JLE, OperandCode::Jvds) },
+ 0x8f => { (Opcode::JG, OperandCode::Jvds) },
x if x < 0xa0 => {
- instruction.opcode = [
+ let op = [
Opcode::SETO,
Opcode::SETNO,
Opcode::SETB,
@@ -1173,90 +927,34 @@ fn read_opcode_0f_map<T: Iterator<Item=u8>>(bytes_iter: &mut T, instruction: &mu
Opcode::SETLE,
Opcode::SETG
][(x & 0xf) as usize];
- Ok(OperandCode::Eb_R0)
- }
- 0xa0 => {
- instruction.opcode = Opcode::PUSH;
- Ok(OperandCode::FS)
- }
- 0xa1 => {
- instruction.opcode = Opcode::POP;
- Ok(OperandCode::GS)
- }
- 0xa2 => {
- instruction.opcode = Opcode::CPUID;
- Ok(OperandCode::Nothing)
- }
- 0xa3 => {
- instruction.opcode = Opcode::BT;
- Ok(OperandCode::Gv_Ev)
- }
- 0xa8 => {
- instruction.opcode = Opcode::PUSH;
- Ok(OperandCode::Nothing)
- }
- 0xa9 => {
- instruction.opcode = Opcode::PUSH;
- Ok(OperandCode::GS)
- }
- 0xae => {
- Ok(OperandCode::ModRM_0x0fae)
- }
- 0xaf => {
- instruction.opcode = Opcode::IMUL;
- Ok(OperandCode::Gv_Ev)
- }
- 0xb0 => {
- instruction.opcode = Opcode::CMPXCHG;
- Ok(OperandCode::Eb_Gb)
- },
- 0xb1 => {
- instruction.opcode = Opcode::CMPXCHG;
- Ok(OperandCode::Ev_Gv)
- }
- 0xb6 => {
- instruction.opcode = Opcode::MOVZX_b;
- Ok(OperandCode::Gv_Eb)
- },
- 0xb7 => {
- instruction.opcode = Opcode::MOVZX_w;
- Ok(OperandCode::Gv_Ew)
- }
- 0xba => {
- Ok(OperandCode::ModRM_0x0fba)
- }
- 0xbb => {
- instruction.opcode = Opcode::BTC;
- Ok(OperandCode::Gv_Ev)
- }
- 0xbc => {
- instruction.opcode = Opcode::BSF;
- Ok(OperandCode::Gv_Ev)
- }
- 0xbd => {
- instruction.opcode = Opcode::BSR;
- Ok(OperandCode::Gv_Ev)
- }
- 0xbe => {
- instruction.opcode = Opcode::MOVSX_b;
- Ok(OperandCode::Gv_Eb)
- }
- 0xbf => {
- instruction.opcode = Opcode::MOVSX_w;
- Ok(OperandCode::Gv_Ew)
- }
- 0xc0 => {
- instruction.opcode = Opcode::XADD;
- Ok(OperandCode::Eb_Gb)
- }
- 0xc1 => {
- instruction.opcode = Opcode::XADD;
- Ok(OperandCode::Ev_Gv)
- }
+ (op, OperandCode::Eb_R0)
+ }
+ 0xa0 => { (Opcode::PUSH, OperandCode::FS) },
+ 0xa1 => { (Opcode::POP, OperandCode::GS) },
+ 0xa2 => { (Opcode::CPUID, OperandCode::Nothing) },
+ 0xa3 => { (Opcode::BT, OperandCode::Gv_Ev) },
+ 0xa8 => { (Opcode::PUSH, OperandCode::Nothing) },
+ 0xa9 => { (Opcode::PUSH, OperandCode::GS) },
+ 0xae => { (Opcode::Invalid, OperandCode::ModRM_0x0fae) },
+ 0xaf => { (Opcode::IMUL, OperandCode::Gv_Ev) },
+ 0xb0 => { (Opcode::CMPXCHG, OperandCode::Eb_Gb) },
+ 0xb1 => { (Opcode::CMPXCHG, OperandCode::Ev_Gv) },
+ 0xb6 => { (Opcode::MOVZX_b, OperandCode::Gv_Eb) },
+ 0xb7 => { (Opcode::MOVZX_w, OperandCode::Gv_Ew) },
+ 0xba => { (Opcode::Invalid, OperandCode::ModRM_0x0fba) },
+ 0xbb => { (Opcode::BTC, OperandCode::Gv_Ev) },
+ 0xbc => { (Opcode::BSF, OperandCode::Gv_Ev) },
+ 0xbd => { (Opcode::BSR, OperandCode::Gv_Ev) },
+ 0xbe => { (Opcode::MOVSX_b, OperandCode::Gv_Eb) },
+ 0xbf => { (Opcode::MOVSX_w, OperandCode::Gv_Ew) },
+ 0xc0 => { (Opcode::XADD, OperandCode::Eb_Gb) },
+ 0xc1 => { (Opcode::XADD, OperandCode::Ev_Gv) },
_ => {
- Err(format!("Unknown opcode: 0f{:x}", b))
+ return Err(format!("Unknown opcode: 0f{:x}", b))
}
- }
+ };
+ instruction.opcode = opcode;
+ Ok(operand_code)
},
None => {
Err("No more bytes".to_owned())
generated by cgit v1.1 at 2024-11-26 17:06:49 +0000