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-rw-r--r--src/long_mode/mod.rs3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index 2935385..abb9723 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -6710,7 +6710,6 @@ fn read_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter: T,
let opwidth = 8;
let modrm = read_modrm(&mut bytes_iter, length)?;
-// println!("mod_bits: {:2b}, r: {:3b}, m: {:3b}", mod_bits, r, m);
instruction.operands[1] = read_E(&mut bytes_iter, instruction, modrm, 4 /* opwidth */, length)?;
instruction.modrm_rrr =
RegSpec::gp_from_parts((modrm >> 3) & 7, instruction.prefixes.rex().r(), opwidth, instruction.prefixes.rex().present());
@@ -6989,7 +6988,6 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter
OperandCode::G_mm_Ew_Ib => {
let modrm = read_modrm(&mut bytes_iter, length)?;
-// println!("mod_bits: {:2b}, r: {:3b}, m: {:3b}", mod_bits, r, m);
instruction.operands[1] = read_E(&mut bytes_iter, instruction, modrm, 4, length)?;
instruction.modrm_rrr =
RegSpec::from_parts((modrm >> 3) & 7, false, RegisterBank::MM);
@@ -7037,7 +7035,6 @@ fn unlikely_operands<T: Iterator<Item=u8>>(decoder: &InstDecoder, mut bytes_iter
let opwidth = imm_width_from_prefixes_64(SizeCode::vqp, instruction.prefixes);
let modrm = read_modrm(&mut bytes_iter, length)?;
-// println!("mod_bits: {:2b}, r: {:3b}, m: {:3b}", mod_bits, r, m);
instruction.operands[1] = read_E(&mut bytes_iter, instruction, modrm, opwidth, length)?;
// `opwidth` can be 2, 4, or 8 here. if opwidth is 2, the first operand is a dword.
// if opwidth is 4, both registers are dwords. and if opwidth is 8, both registers are