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-rw-r--r--src/long_mode/mod.rs10
-rw-r--r--src/protected_mode/mod.rs13
-rw-r--r--src/real_mode/mod.rs17
3 files changed, 28 insertions, 12 deletions
diff --git a/src/long_mode/mod.rs b/src/long_mode/mod.rs
index dee759d..97ac8d1 100644
--- a/src/long_mode/mod.rs
+++ b/src/long_mode/mod.rs
@@ -6005,7 +6005,7 @@ fn read_M<
sink.record(
modrm_start + 6,
modrm_start + 7,
- InnerDescription::Misc("mmm field is a simple register dereference (mod bits: 00)")
+ InnerDescription::Misc("memory operand is [reg] with no displacement, register selected by `mmm` (mod bits: 00)")
.with_id(modrm_start + 0)
);
OperandSpec::Deref
@@ -7643,7 +7643,13 @@ fn read_with_annotations<
0x26 |
0x2e |
0x36 |
- 0x3e =>{ /* no-op in amd64 */ },
+ 0x3e => {
+ /* no-op in amd64 */
+ sink.record((words.offset() - 2) as u32 * 8, (words.offset() - 2) as u32 * 8 + 7, FieldDescription {
+ desc: InnerDescription::Misc("ignored prefix in 64-bit mode"),
+ id: words.offset() as u32 * 8 - 16,
+ });
+ },
0x64 => {
sink.record((words.offset() - 2) as u32 * 8, (words.offset() - 2) as u32 * 8 + 7, FieldDescription {
desc: InnerDescription::SegmentPrefix(Segment::FS),
diff --git a/src/protected_mode/mod.rs b/src/protected_mode/mod.rs
index 422f6d9..10a9248 100644
--- a/src/protected_mode/mod.rs
+++ b/src/protected_mode/mod.rs
@@ -5902,7 +5902,7 @@ fn read_M_16bit<
sink.record(
modrm_start + 6,
modrm_start + 7,
- InnerDescription::Misc("mmm selects a dereference with no displacement (mod bits: 00)")
+ InnerDescription::Misc("memory operand is [reg(s)] with no displacement, register(s) selected by `mmm` (mod bits: 00)")
.with_id(modrm_start + 0)
);
if mmm > 3 {
@@ -5918,7 +5918,7 @@ fn read_M_16bit<
sink.record(
modrm_start + 6,
modrm_start + 7,
- InnerDescription::Misc("mmm selects registers for deref address with 8-bit displacement (mod bits: 01)")
+ InnerDescription::Misc("memory operand is [reg(s)+disp8] indexed by register(s) selected by `mmm` (mod bits: 01)")
.with_id(modrm_start + 0)
);
sink.record(
@@ -5948,7 +5948,7 @@ fn read_M_16bit<
sink.record(
modrm_start + 6,
modrm_start + 7,
- InnerDescription::Misc("mmm selects registers for deref address with 16-bit displacement (mod bits: 10)")
+ InnerDescription::Misc("memory operand is [reg(s)+disp16] indexed by register(s) selected by `mmm` (mod bits: 01)")
.with_id(modrm_start + 0)
);
sink.record(
@@ -6027,7 +6027,7 @@ fn read_M<
sink.record(
modrm_start + 6,
modrm_start + 7,
- InnerDescription::Misc("mmm field is a simple register dereference (mod bits: 00)")
+ InnerDescription::Misc("memory operand is [reg] with no displacement, register selected by `mmm` (mod bits: 00)")
.with_id(modrm_start + 0)
);
OperandSpec::Deref
@@ -7721,6 +7721,11 @@ fn read_operands<
T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpeax_arch::Arch>::Word>,
S: DescriptionSink<FieldDescription>
>(decoder: &InstDecoder, words: &mut T, instruction: &mut Instruction, operand_code: OperandCode, sink: &mut S) -> Result<(), DecodeError> {
+ sink.record(
+ words.offset() as u32 * 8 - 1, words.offset() as u32 * 8 - 1,
+ InnerDescription::Boundary("opcode ends/operands begin (typically)")
+ .with_id(words.offset() as u32 * 8 - 1)
+ );
let modrm_start = words.offset() as u32 * 8;
let opcode_start = modrm_start - 8;
instruction.operands[0] = OperandSpec::RegRRR;
diff --git a/src/real_mode/mod.rs b/src/real_mode/mod.rs
index 3d78fa3..d43005e 100644
--- a/src/real_mode/mod.rs
+++ b/src/real_mode/mod.rs
@@ -5902,7 +5902,7 @@ fn read_M_16bit<
sink.record(
modrm_start + 6,
modrm_start + 7,
- InnerDescription::Misc("mmm selects a dereference with no displacement (mod bits: 00)")
+ InnerDescription::Misc("memory operand is [reg(s)] with no displacement, register(s) selected by `mmm` (mod bits: 00)")
.with_id(modrm_start + 0)
);
if mmm > 3 {
@@ -5918,7 +5918,7 @@ fn read_M_16bit<
sink.record(
modrm_start + 6,
modrm_start + 7,
- InnerDescription::Misc("mmm selects registers for deref address with 8-bit displacement (mod bits: 01)")
+ InnerDescription::Misc("memory operand is [reg(s)+disp8] indexed by register(s) selected by `mmm` (mod bits: 01)")
.with_id(modrm_start + 0)
);
sink.record(
@@ -5948,7 +5948,7 @@ fn read_M_16bit<
sink.record(
modrm_start + 6,
modrm_start + 7,
- InnerDescription::Misc("mmm selects registers for deref address with 16-bit displacement (mod bits: 10)")
+ InnerDescription::Misc("memory operand is [reg(s)+disp16] indexed by register(s) selected by `mmm` (mod bits: 01)")
.with_id(modrm_start + 0)
);
sink.record(
@@ -6029,7 +6029,7 @@ fn read_M<
sink.record(
modrm_start + 6,
modrm_start + 7,
- InnerDescription::Misc("mmm field is a simple register dereference (mod bits: 00)")
+ InnerDescription::Misc("memory operand is [reg] with no displacement, register selected by `mmm` (mod bits: 00)")
.with_id(modrm_start + 0)
);
OperandSpec::Deref
@@ -6039,7 +6039,7 @@ fn read_M<
sink.record(
modrm_start + 6,
modrm_start + 7,
- InnerDescription::Misc("memory operand is [reg+disp8] indexed by register(s) selected by `mmm` (mod bits: 01)")
+ InnerDescription::Misc("memory operand is [reg+disp8] indexed by register selected by `mmm` (mod bits: 01)")
.with_id(modrm_start + 0)
);
read_num(words, 1)? as i8 as i32
@@ -6047,7 +6047,7 @@ fn read_M<
sink.record(
modrm_start + 6,
modrm_start + 7,
- InnerDescription::Misc("memory operand is [reg+disp16] indexed by register(s) selected by `mmm` (mod bits: 10)")
+ InnerDescription::Misc("memory operand is [reg+disp32] indexed by register(s) selected by `mmm` (mod bits: 10)")
.with_id(modrm_start + 0)
);
read_num(words, 4)? as i32
@@ -7723,6 +7723,11 @@ fn read_operands<
T: Reader<<Arch as yaxpeax_arch::Arch>::Address, <Arch as yaxpeax_arch::Arch>::Word>,
S: DescriptionSink<FieldDescription>
>(decoder: &InstDecoder, words: &mut T, instruction: &mut Instruction, operand_code: OperandCode, sink: &mut S) -> Result<(), DecodeError> {
+ sink.record(
+ words.offset() as u32 * 8 - 1, words.offset() as u32 * 8 - 1,
+ InnerDescription::Boundary("opcode ends/operands begin (typically)")
+ .with_id(words.offset() as u32 * 8 - 1)
+ );
let modrm_start = words.offset() as u32 * 8;
let opcode_start = modrm_start + 8;
instruction.operands[0] = OperandSpec::RegRRR;
generated by cgit v1.1 at 2024-11-22 22:47:05 +0000