diff options
Diffstat (limited to 'test/real_mode/mod.rs')
| -rw-r--r-- | test/real_mode/mod.rs | 136 |
1 files changed, 136 insertions, 0 deletions
diff --git a/test/real_mode/mod.rs b/test/real_mode/mod.rs index af5a315..b8a636c 100644 --- a/test/real_mode/mod.rs +++ b/test/real_mode/mod.rs @@ -16712,6 +16712,142 @@ fn test_real_mode() { test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); + test_invalid(&[0x62, 0xf1, 0x7c, 0x8d, 0x11, 0x0a]); + test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x12, 0xca]); // no broadcast + test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x16, 0xca]); // + test_invalid(&[0x62, 0xf1, 0x7c, 0xbd, 0x28, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf1, 0x7c, 0x9d, 0x29, 0xca]); // no sae/er support on movaps + test_invalid(&[0x62, 0xf1, 0x7c, 0x38, 0x2b, 0x0a]); // no zero mask-merge + test_invalid(&[0x62, 0xf1, 0x7c, 0xa8, 0x2b, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf1, 0xfc, 0x28, 0x2b, 0x0a]); // no W=1 + test_invalid(&[0x62, 0xf1, 0x7c, 0x18, 0x2e, 0x0a]); // no broadcast from memory + test_invalid(&[0x62, 0xf1, 0x7d, 0x68, 0x2e, 0x0a]); // no L'L=11 + test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x2e, 0x0a]); // no zero mask-merge + test_invalid(&[0x62, 0xf1, 0xfc, 0xfd, 0x51, 0xca]); // requires W=0 + test_invalid(&[0x62, 0xf1, 0xfc, 0x78, 0x5a, 0xca]); // W=0 + test_invalid(&[0x62, 0xf1, 0x7c, 0xb8, 0xc2, 0x0a, 0xcc]); // no zero mask-merge + test_invalid(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0xca, 0xcc]); // no broadcast from register source + test_invalid(&[0x62, 0xf1, 0xfd, 0xdd, 0x10, 0x0a]); + test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0x14, 0xca]); // no broadcast in reg-reg + test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0x15, 0xca]); // no broadcast in reg-reg + test_invalid(&[0x62, 0xf1, 0xfd, 0x38, 0x28, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf1, 0xfd, 0x18, 0x2b, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x2b, 0x0a]); // no zero mask-merge + test_invalid(&[0x62, 0xf1, 0x7d, 0x08, 0x2b, 0x0a]); // no W=- + test_invalid(&[0x62, 0xf1, 0xfd, 0x79, 0x2e, 0xca]); // mask reg must be 000 + test_invalid(&[0x62, 0xf1, 0xfd, 0x18, 0x2e, 0x0a]); // no broadcast from memory + test_invalid(&[0x62, 0xf1, 0xfd, 0x68, 0x2e, 0x0a]); // no L'L=11 + test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x2e, 0x0a]); // no zero mask-merge + test_invalid(&[0x62, 0xf1, 0xfd, 0x28, 0x5b, 0xca]); // no W=1 + test_invalid(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0xca]); // no broadcast on reg operand (no sae) + test_invalid(&[0x62, 0xf1, 0xfd, 0x88, 0x6e, 0xca]); //no zero mask-merge + test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x6e, 0xca]); // no zero mask-merge + test_invalid(&[0x62, 0xf1, 0x7d, 0x88, 0x7e, 0xca]); // no zero mask-merge + test_invalid(&[0x62, 0xf1, 0xfd, 0xbd, 0xc2, 0x0a, 0xcc]); // no zero mask-merge + test_invalid(&[0x62, 0xf1, 0x7d, 0x78, 0xe6, 0xca]); // requires W=1 + test_invalid(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0xca]); // no reg-reg encoding + test_invalid(&[0x62, 0xf1, 0xfd, 0x38, 0xf6, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf1, 0xfd, 0xa8, 0xf6, 0x0a]); // no zero mask-merge + test_invalid(&[0x62, 0xf1, 0x7e, 0x6d, 0x10, 0x0a]); + test_invalid(&[0x62, 0xf1, 0x7e, 0x6f, 0x10, 0x0a]); + test_invalid(&[0x62, 0xf1, 0x7e, 0x38, 0x10, 0x0a]); + test_invalid(&[0x62, 0xf1, 0x7e, 0x3d, 0x11, 0xca]); + test_invalid(&[0x62, 0xf1, 0x7e, 0xad, 0x11, 0x0a]); + test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2a, 0xca]); // mask reg must be 000 + test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2a, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2a, 0x0a]); // no L'L=11 + test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2c, 0xca]); // mask register must be 000 + test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2c, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf1, 0x7e, 0x38, 0x2c, 0x0a]); // no broadcast, regardless of W + test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2c, 0x0a]); // no L'L=11 + test_invalid(&[0x62, 0xf1, 0xfe, 0x29, 0x2d, 0xca]); // mask register must be 000 + test_invalid(&[0x62, 0xf1, 0xfe, 0x38, 0x2d, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x2d, 0x0a]); // no L'L=11 + test_invalid(&[0x62, 0xf1, 0x7e, 0x78, 0x5a, 0x0a]); // no broadcast with memory source + test_invalid(&[0x62, 0xf1, 0xfe, 0x68, 0x7b, 0x0a]); // no L'L=11 + test_invalid(&[0x62, 0xf1, 0xfe, 0x88, 0x7e, 0xca]); // no zero mask-merge + test_invalid(&[0x62, 0xf1, 0x7e, 0x6d, 0xc2, 0xca, 0xcc]); // do not allow L'L=11 + test_invalid(&[0x62, 0xf1, 0xff, 0x6d, 0x10, 0x0a]); + test_invalid(&[0x62, 0xf1, 0xff, 0x6f, 0x10, 0x0a]); + test_invalid(&[0x62, 0xf1, 0xff, 0x3d, 0x11, 0xca]); + test_invalid(&[0x62, 0xf1, 0xff, 0xad, 0x11, 0x0a]); + test_invalid(&[0x62, 0xf1, 0xff, 0xbd, 0x12, 0x0a]); + test_invalid(&[0x62, 0xf1, 0xff, 0x38, 0x51, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf1, 0xff, 0x68, 0x51, 0x0a]); // no L'L=11 + test_invalid(&[0x62, 0xf1, 0xff, 0xbd, 0x5a, 0x0a]); // no L'L=11 unless for sae + test_invalid(&[0x62, 0xf1, 0xff, 0x6f, 0x5a, 0x0a]); // no L'L=11 unless for sae + test_invalid(&[0x62, 0xf1, 0x7f, 0x78, 0x5f, 0xca]); // requires W=1 + test_invalid(&[0x62, 0xf1, 0xff, 0x68, 0x7b, 0x0a]); // no L'L=11 + test_invalid(&[0x62, 0xf1, 0xff, 0x6d, 0xc2, 0x0a, 0xcc]); // no L'L=11 + test_invalid(&[0x62, 0xf2, 0xfd, 0x78, 0x13, 0x0a]); // W=0 + test_invalid(&[0x62, 0xf2, 0x7d, 0xbd, 0x14, 0xca]); // no broadcast + test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x25, 0xca]); // W must be 1 + test_invalid(&[0x62, 0xf2, 0xfd, 0xcd, 0x25, 0xca]); + test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x26, 0x0a]); // no zero-merge + test_invalid(&[0x62, 0xf2, 0x7d, 0xad, 0x26, 0x0a]); // no zero-merge + test_invalid(&[0x62, 0xf2, 0x7d, 0xdd, 0x27, 0x0a]); // no zero-merge + test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0xca]); // no invalid broadcast mode + test_invalid(&[0x62, 0xf2, 0xfd, 0xdd, 0x27, 0x0a]); // no zero-merge + test_invalid(&[0x62, 0xf2, 0xfd, 0xbd, 0x28, 0xca]); // no broadcast on register source + test_invalid(&[0x62, 0xf2, 0xfd, 0xad, 0x29, 0xca]); // no zero-merge + test_invalid(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0xca]); // no zero-merge + test_invalid(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0xca]); // no register source + test_invalid(&[0x62, 0xf2, 0x7d, 0xa8, 0x2a, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf2, 0x7d, 0xfd, 0x2d, 0x0a]); // sae is indicated by evex.b, with memory source evex.b implies broadcast as well. vscalefss does not broadcast, so reject. + test_invalid(&[0x62, 0xf2, 0x7d, 0xbd, 0x43, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x4d, 0xca]); // no sae + test_invalid(&[0x62, 0xf2, 0x7d, 0x6d, 0x4d, 0xca]); // no L'L=11 + test_invalid(&[0x62, 0xf2, 0x7d, 0x3d, 0x4e, 0xca]); // no sae + test_invalid(&[0x62, 0xf2, 0x7d, 0x68, 0x4f, 0xca]); // no L'L=11 + test_invalid(&[0x62, 0xf2, 0x7d, 0xad, 0x63, 0x0a]); // no zero-merge on memory operands + test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x78, 0xca]); // deny evex.b + test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x7a, 0xca]); // still no evex.b + test_invalid(&[0x62, 0xf2, 0x7d, 0x38, 0x7c, 0xca]); // no broadcast here either + test_display(&[0x62, 0xf2, 0x7d, 0x68, 0x99, 0xca], "vfmadd132ss xmm1, xmm0, xmm2"); // no L'L==0 when not sae + test_invalid(&[0x62, 0xf2, 0xfd, 0x38, 0xdc, 0x0a]); // no broadcast + test_invalid(&[0x62, 0xf2, 0xfd, 0xa8, 0xdc, 0x0a]); // no zero mask-merge + test_invalid(&[0x62, 0xf2, 0x7e, 0xad, 0x10, 0x0a]); // cannot set evex.z on stores. + test_invalid(&[0x62, 0xf2, 0x7e, 0xcd, 0x12, 0x0a]); + test_invalid(&[0x62, 0xf2, 0x7e, 0x88, 0x28, 0xca]); // + test_invalid(&[0x62, 0xf2, 0x7e, 0xa8, 0x39, 0xca]); // no zero mask-merge + test_invalid(&[0x62, 0xf2, 0x7e, 0x88, 0x3a, 0xca]); // no zero "mask merge", no masking at all + test_invalid(&[0x62, 0xf2, 0x7e, 0xbd, 0x72, 0xca]); // no register-register broadcast + test_display(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0xca], "vp2intersectd k1, xmm0, xmm2"); // VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX + test_invalid(&[0x62, 0xf2, 0x7f, 0x09, 0x68, 0xca]); // requires mask reg to be 000 + test_invalid(&[0x62, 0xf2, 0xff, 0x09, 0x68, 0xca]); // requires mask reg to be 000 + test_invalid(&[0x62, 0xf3, 0xfd, 0xbd, 0x00, 0xca, 0xcc]); // no broadcast on reg-reg ops + test_invalid(&[0x62, 0xf3, 0x7d, 0xbd, 0x04, 0xca, 0xcc]); // no broadcast on reg sources + test_invalid(&[0x62, 0xf3, 0x7d, 0x5d, 0x0a, 0x0a, 0xcc]); // no broadcast with memory source + test_invalid(&[0x62, 0xf3, 0x7d, 0x6d, 0x0a, 0x0a, 0xcc]); // no broadcast with memory source + test_invalid(&[0x62, 0xf3, 0xfd, 0xa8, 0x0b, 0xca, 0xcc]); // no zero-merge without mask reg + test_invalid(&[0x62, 0xf3, 0xfd, 0x38, 0x0b, 0x0a, 0xcc]); // no broadcast on memory source + test_invalid(&[0x62, 0xf3, 0xfd, 0x68, 0x0b, 0x0a, 0xcc]); // L'L==11 requires sae + test_invalid(&[0x62, 0xf3, 0xfd, 0x3d, 0x0f, 0xca, 0xcc]); // no broadcast + test_invalid(&[0x62, 0xf3, 0xfd, 0x38, 0x0f, 0x0a, 0xcc]); // still no broadcast + test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x14, 0xca, 0xcc]); // no zero mask-merge, no masking! + test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x14, 0xca, 0xcc]); // no broadcast + test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x15, 0xca, 0xcc]); // no broadcast + test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x15, 0xca, 0xcc]); // no zero mask-merge + test_invalid(&[0x62, 0xf3, 0x7d, 0x18, 0x16, 0xca, 0xcc]); // no broadcast + test_invalid(&[0x62, 0xf3, 0x7d, 0x88, 0x16, 0xca, 0xcc]); // no zero mask-merge + test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x17, 0xca, 0xcc]); // no broadcast + test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x17, 0xca, 0xcc]); // no zero mask-merge + test_invalid(&[0x62, 0xf3, 0x7d, 0x3d, 0x19, 0x0a, 0xcc]); // no zero-merge with memmory dest + test_invalid(&[0x62, 0xf3, 0x7d, 0xcd, 0x1b, 0x0a, 0xcc]); // no zero-merge into memory + test_invalid(&[0x62, 0xf3, 0x7d, 0x3d, 0x1d, 0x0a, 0xcc]); // no zero-merge into memory + test_invalid(&[0x62, 0xf3, 0x7d, 0x6d, 0x1d, 0x0a, 0xcc]); // no L'L==11 for non-sae + test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x20, 0xca, 0xcc]); // + test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x20, 0xca, 0xcc]); // + test_invalid(&[0x62, 0xf3, 0x7d, 0x18, 0x21, 0xca, 0xcc]); // + test_invalid(&[0x62, 0xf3, 0x7d, 0x88, 0x21, 0xca, 0xcc]); // + test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x22, 0xca, 0xcc]); // + test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x22, 0xca, 0xcc]); // + test_invalid(&[0x62, 0xf3, 0x7d, 0xad, 0x3e, 0xca, 0xcc]); // no zero mask-merge + test_invalid(&[0x62, 0xf3, 0x7d, 0x38, 0x42, 0x0a, 0xcc]); // no broadcast + test_invalid(&[0x62, 0xf3, 0xfd, 0x29, 0x44, 0xca, 0xcc]); // mask reg must be 000 + test_invalid(&[0x62, 0xf3, 0xfd, 0x18, 0x44, 0x0a, 0xcc]); // + test_invalid(&[0x62, 0xf3, 0xfd, 0x88, 0x44, 0x0a, 0xcc]); // + test_invalid(&[0x62, 0xf3, 0xfd, 0xbd, 0x66, 0x0a, 0xcc]); // no zero mask-merge test_display(&[0x63, 0xc1], "arpl cx, ax"); test_display(&[0x65, 0x66, 0x0f, 0x01, 0xdc], "stgi"); test_display(&[0x65, 0x66, 0x66, 0x64, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword fs:[bx]"); |