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2023-12-16fix hreset being disassembled as having second operand of "Nothing"iximeow
2023-12-16fix incorrect register class names in long_mode1.2.1iximeow
2023-12-16fix incorrect register selection for `vpbroadcastm{b2q,w2d}` with `rex.b` setiximeow
2023-12-16fix incorrect register selection for `vpmov*2m` with `rex.r` setiximeow
2023-12-16fix incorrect register selection for `vpmovm2*` with `rex.b` setiximeow
2023-12-16abnormal memory sizes for keylocker instructions are not bugsiximeow
2023-12-16reword new changelog entriesiximeow
2023-12-16fix opportunity for unhandled register synonymsiximeow
2023-12-15update changelog, bump version number for future publishiximeow
2023-12-15more RegSpec constructor validation, fix bug in x86_64 1b reg specsiximeow
2023-12-15fix incorrect register numbers in r12/r13 RegSpec constructor functionsDongjia "toka" Zhang
2023-07-241.2.0 (Cargo.toml this time)1.2.0iximeow
2023-07-241.2.0iximeow
2023-07-24fix handling of lar/lsl source registeriximeow
2023-07-23fix inconsistently-poreted memory access size of vcvt{,t}{sd,si}iximeow
2023-07-23fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit)iximeow
2023-07-16a few notes before calling this [somewhat substantial] refactor doneiximeow
2023-07-16forward changes along to 16-bit decoder...iximeow
2023-07-16fix indentationiximeow
2023-07-16unify 64-/32-bit moreiximeow
2023-07-16forward changes along to 32-bit decoder...iximeow
2023-07-09re-enable tests, pretty sure ive squeezed out as much opt as im getting right...iximeow
2023-07-09trying to delete branches on bank sizeiximeow
2023-07-09more matches to be mad at and turn into lookups insteadiximeow
2023-07-09irritated at matchesiximeow
2023-07-09that doesnt need to be a transmuteiximeow
2023-07-09changing OpcodeRecord to avoid bad use of simdiximeow
2023-07-09smaller tables and err variants preserves perf, but less code/dataiximeow
2023-07-09table-izing these matches substantially helps (pending bugs...)iximeow
2023-07-09remove very done todoiximeow
2023-07-09bitpacking is_memory seems to help (surpisingly much!)iximeow
2023-07-09Revert "restructuring of hotpath code, not worse but not better"iximeow
2023-07-09restructuring of hotpath code, not worse but not betteriximeow
2023-07-08consistently report end of prefixes/start of opcodeiximeow
2023-07-08todo for 2.xiximeow
2023-07-08seems like this makes things a bit faster...?iximeow
2023-07-08move rip-rel check to a slightly colder spot...iximeow
2023-07-08annotation ordering changed a bit in refactoring, for the better???iximeow
2023-07-08actually reject lock prefixes in vex instructionsiximeow
2023-07-08fix v(p)gather situations, get vex tests passing againiximeow
2023-07-06defer assigning mem_size or operand_count tooiximeow
2023-07-06M_Gv should be unreachable too...iximeow
2023-07-06defer initial assignment of regs and operands as much as possibleiximeow
2023-07-05fix operand handling for the psl/psr family of xmm shifts/rotatesiximeow
2023-07-05re-correct operand order of movdq2qiximeow
2023-07-04more read_E hoistingiximeow
2023-07-04regalloc magic? no useful diff but better perf. 49.61cpi (2233ms)iximeow
2023-07-04two more test casesiximeow
2023-07-04incidental cleanup, see if inlining in evex helps/hurts (it hurts)iximeow
2023-07-04fix xbegin/xend (broken in DecodeCtx::rrr)iximeow