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2020-05-21add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensionsiximeow
also add builders to get decoders appropriate for specific microarchitectures from intel and amd * low-power architectures are not yet present
2020-05-03bump version to 0.0.110.0.11iximeow
2020-05-03"is there a rep prefix" is something people need to be able to askiximeow
2020-05-03add width() to ask width of an x86 operandiximeow
this is largely wrong for memory operands, which require more invasive changes
2020-05-03that instruction is cwd, not cbdiximeow
2020-05-03bump yaxpeax-arch to 0.0.4, use AddressDiff, fix warnings in ffiiximeow
2020-03-23update docs to not be long_mode-specificiximeow
2020-03-22bump to 0.0.10 to fix a warning0.0.10iximeow
2020-03-22bump version to 0.0.90.0.9iximeow
2020-03-22yaxpeax-x86 decodes in 32-bit mode nowiximeow
2020-02-22include reference to changelog in readme0.0.8iximeow
also bump to 0.0.8 and hope this is the right crates.io incantation to show the readme there
2020-02-22bump to 0.0.70.0.7iximeow
2020-02-22remove unused functioniximeow
2020-02-22explicitly report x87 as not (yet) supportediximeow
2020-02-22swap pronoun for nouniximeow
2020-02-22support most avx operand codesiximeow
avx is still incomplete, but less so avx is still practically untested
2020-02-22fix {jmp,call} <reg>, as well as jmpf/callfiximeow
also support vmxon to finish out the f30f opcode map add tests for forms of inc/dec, as well as TODOs, as yaxpeax-x86 doesn't provide a way to distinguish different operand sizes (yet)
2020-02-22more sse/sse2 supportiximeow
largely f20f/f30f opcode map items
2020-02-22add vmclear testiximeow
this instruction is decoded with the sse2 660f map but not actually added in sse2
2020-02-22support 660f sse2 instructionsiximeow
this isn't quite all of sse2, but gets close. the f20f opcode map still needs some touching up. also fix `G_E_xmm_Ib` not respecting rex.r for the rrr operand
2020-02-16bump version0.0.6iximeow
2020-02-16embarassingly had OperandSpec variants for modrm displacement == 0 backwardsiximeow
2020-02-11bump to 0.0.50.0.5iximeow
2020-02-11support `in` and `out` instructionsiximeow
2020-02-11add `RegSpec::name` to get `&'static str` labels for registersiximeow
2020-02-11derive Ord and PartialOrd for RegSpec and RegisterBankiximeow
this makes these usable as keys in collections such as BTreeMap. there is no specific ordering imposed by Ord (f.ex it may be the case that `eax > dx` while `eax > rax`), but some specific ordering may be imposed in the future.
2020-02-06bump yaxpeax-arch version0.0.4iximeow
2020-01-18bump yaxpeax-archiximeow
2020-01-15oh no, first version bump alreadyiximeow
2020-01-15support "int imm8" instructionsiximeow
2020-01-15update yaxpeax-arch dependency because it is a crate now!iximeow
2020-01-15update readme with no-std information, feature description, and some numbersiximeow
2020-01-15make space for non-64bit modesiximeow
2020-01-15avoid needing to dynamically allocate in yaxpeax-x86 ffiiximeow
this makes ffi builds also no-std, and significantly smaller too
2020-01-15make x86 actually no_stdiximeow
it depended on crates that dragged in std, oops
2020-01-15add more sse2 instructions (packed shift by immediate, mostly)iximeow
really need to adjust OperandCode, almost out of one-off options...
2020-01-15add 660f6* series instructions as well as 660f70iximeow
this adds in some missing sse2 instructions in the alternate secondary opcode map. because these were missing, instructions were incorrectly decoded from the 0f opcode map, yielding mmx-operand versions of themselves (usually) there are undoubtedly more missing sse2 instructions from the 660f map.
2020-01-15negative displacements were printed wrong, test against that for the futureiximeow
this was accidentally fixed in no_std-ing, the prior commit
2020-01-15no_std!!iximeow
this makes yaxpeax-x86 no_std. no externally-visible changes!
2020-01-13explicitly fail to handle WAIT prefixiximeow
2020-01-13test that instruction lengths are correctiximeow
fix several instances of incorrect instruction lengths * immediates for `mov reg, imm` and some other instructions were double-counted * lengths for vex prefixes were wrong all over the place
2020-01-13add Default impl for Instruction to track yaxpeax-archiximeow
2020-01-13de-pub some internal functionsiximeow
2020-01-12forgot a line breakiximeow
2020-01-12update descriptioniximeow
2020-01-12update repository path and explicitly version depsiximeow
2020-01-12add explicit license alsoiximeow
2020-01-12add readme, finallyiximeow
2020-01-12no println when decoding vex instructions pleaseiximeow
2020-01-12add *extremely* poor ffi bindings for x86 decodersiximeow
this is specifically to support a disas-bench integration, for now
generated by cgit v1.1 at 2024-11-05 21:23:31 +0000