| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-12-16 | fix incorrect register selection for `vpmov*2m` with `rex.r` set | iximeow | |
| 2023-12-16 | fix incorrect register selection for `vpmovm2*` with `rex.b` set | iximeow | |
| 2023-12-16 | abnormal memory sizes for keylocker instructions are not bugs | iximeow | |
| new `does_not_decode_invalid_registers` fuzzer found other bugs! the 384-bit accesses for 128b keylocker instructions are an otherwise-unknown size and had a memory size of `BUG`. they are not bugs. give the memory size a real name. | |||
| 2023-12-16 | reword new changelog entries | iximeow | |
| 2023-12-16 | fix opportunity for unhandled register synonyms | iximeow | |
| registers `al`, `cl`, `dl`, and `bl` could have two different representations - with `rex.w` and without. these two forms of `RegSpec` would not compare equal, nor has the same, so for code relying on `RegSpec` to faithfully represent a 1-1 mapping to x86 registers, these synonyms would introduce bugs in register analysis. for example, in `yaxpeax-core`, this would result in instructions writing to `rex.w al` not being visible as definitions for a future read of `!rex.w al`. fix this in `x86_64` code, add new test cases about the confusion, adjust register names to make this situation more clearly a bug, and introduce two new fuzz targets that would have helped spot this error. | |||
| 2023-12-15 | update changelog, bump version number for future publish | iximeow | |
| 2023-12-15 | more RegSpec constructor validation, fix bug in x86_64 1b reg specs | iximeow | |
| * the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be constructed in two ways that produce "identical" `RegSpec` that are.. not. e.g. `RegSpec::al() != Regspec::rb(0)` even though `RegSpec::al().name() == RegSpec::rb(0).name()`. this corrects the `rb` constructor at least, but instructions like `4830c0` and `30c0` still produce incompatible versions of `al`. * also fix register numbering used explicit qword-sized RegSpec constructors, r12 and r13 used to produce r8 and r9 | |||
| 2023-12-15 | fix incorrect register numbers in r12/r13 RegSpec constructor functions | Dongjia "toka" Zhang | |
| these functions had a copypaste error where the r12 and r13 versions would create RegSpec for registers 8 and 9 instead of 12 and 13. use correct register numbers in these macros. | |||
| 2023-07-24 | 1.2.0 (Cargo.toml this time)1.2.0 | iximeow | |
| 2023-07-24 | 1.2.0 | iximeow | |
| 2023-07-24 | fix handling of lar/lsl source register | iximeow | |
| 2023-07-23 | fix inconsistently-poreted memory access size of vcvt{,t}{sd,si} | iximeow | |
| 2023-07-23 | fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit) | iximeow | |
| 2023-07-16 | a few notes before calling this [somewhat substantial] refactor done | iximeow | |
| 2023-07-16 | forward changes along to 16-bit decoder... | iximeow | |
| 2023-07-16 | fix indentation | iximeow | |
| 2023-07-16 | unify 64-/32-bit more | iximeow | |
| 2023-07-16 | forward changes along to 32-bit decoder... | iximeow | |
| 2023-07-09 | re-enable tests, pretty sure ive squeezed out as much opt as im getting ↵ | iximeow | |
| right now... | |||
| 2023-07-09 | trying to delete branches on bank size | iximeow | |
| 2023-07-09 | more matches to be mad at and turn into lookups instead | iximeow | |
| 2023-07-09 | irritated at matches | iximeow | |
| 2023-07-09 | that doesnt need to be a transmute | iximeow | |
| 2023-07-09 | changing OpcodeRecord to avoid bad use of simd | iximeow | |
| 2023-07-09 | smaller tables and err variants preserves perf, but less code/data | iximeow | |
| 2023-07-09 | table-izing these matches substantially helps (pending bugs...) | iximeow | |
| 2023-07-09 | remove very done todo | iximeow | |
| 2023-07-09 | bitpacking is_memory seems to help (surpisingly much!) | iximeow | |
| 2023-07-09 | Revert "restructuring of hotpath code, not worse but not better" | iximeow | |
| This reverts commit 15c821a2d3fbf2fc0458090b6cc12f2ac093f075. | |||
| 2023-07-09 | restructuring of hotpath code, not worse but not better | iximeow | |
| 2023-07-08 | consistently report end of prefixes/start of opcode | iximeow | |
| 2023-07-08 | todo for 2.x | iximeow | |
| 2023-07-08 | seems like this makes things a bit faster...? | iximeow | |
| 2023-07-08 | move rip-rel check to a slightly colder spot... | iximeow | |
| 2023-07-08 | annotation ordering changed a bit in refactoring, for the better??? | iximeow | |
| 2023-07-08 | actually reject lock prefixes in vex instructions | iximeow | |
| 2023-07-08 | fix v(p)gather situations, get vex tests passing again | iximeow | |
| 2023-07-06 | defer assigning mem_size or operand_count too | iximeow | |
| 2023-07-06 | M_Gv should be unreachable too... | iximeow | |
| 2023-07-06 | defer initial assignment of regs and operands as much as possible | iximeow | |
| not a huge improvement, but something | |||
| 2023-07-05 | fix operand handling for the psl/psr family of xmm shifts/rotates | iximeow | |
| these instructions ignored rex bits even for xmm reigsters, which is incorrect (so says xed) | |||
| 2023-07-05 | re-correct operand order of movdq2q | iximeow | |
| 2023-07-04 | more read_E hoisting | iximeow | |
| 2023-07-04 | regalloc magic? no useful diff but better perf. 49.61cpi (2233ms) | iximeow | |
| 2023-07-04 | two more test cases | iximeow | |
| 2023-07-04 | incidental cleanup, see if inlining in evex helps/hurts (it hurts) | iximeow | |
| 2023-07-04 | fix xbegin/xend (broken in DecodeCtx::rrr) | iximeow | |
| 2023-07-04 | finally delete top-level modrm (50.10cpi, 2322ms) | iximeow | |
| 2023-07-04 | begin project to hoist all read_E (perf better again! 50.21cpi) | iximeow | |
| 2023-07-04 | fix f6 test imm lengths (perf regression :( ) | iximeow | |
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