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2023-07-23fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit)iximeow
2023-07-16a few notes before calling this [somewhat substantial] refactor doneiximeow
2023-07-16forward changes along to 16-bit decoder...iximeow
2023-07-16fix indentationiximeow
2023-07-16unify 64-/32-bit moreiximeow
2023-07-16forward changes along to 32-bit decoder...iximeow
2023-07-09re-enable tests, pretty sure ive squeezed out as much opt as im getting ↵iximeow
right now...
2023-07-09trying to delete branches on bank sizeiximeow
2023-07-09more matches to be mad at and turn into lookups insteadiximeow
2023-07-09irritated at matchesiximeow
2023-07-09that doesnt need to be a transmuteiximeow
2023-07-09changing OpcodeRecord to avoid bad use of simdiximeow
2023-07-09smaller tables and err variants preserves perf, but less code/dataiximeow
2023-07-09table-izing these matches substantially helps (pending bugs...)iximeow
2023-07-09remove very done todoiximeow
2023-07-09bitpacking is_memory seems to help (surpisingly much!)iximeow
2023-07-09Revert "restructuring of hotpath code, not worse but not better"iximeow
This reverts commit 15c821a2d3fbf2fc0458090b6cc12f2ac093f075.
2023-07-09restructuring of hotpath code, not worse but not betteriximeow
2023-07-08consistently report end of prefixes/start of opcodeiximeow
2023-07-08todo for 2.xiximeow
2023-07-08seems like this makes things a bit faster...?iximeow
2023-07-08move rip-rel check to a slightly colder spot...iximeow
2023-07-08annotation ordering changed a bit in refactoring, for the better???iximeow
2023-07-08actually reject lock prefixes in vex instructionsiximeow
2023-07-08fix v(p)gather situations, get vex tests passing againiximeow
2023-07-06defer assigning mem_size or operand_count tooiximeow
2023-07-06M_Gv should be unreachable too...iximeow
2023-07-06defer initial assignment of regs and operands as much as possibleiximeow
not a huge improvement, but something
2023-07-05fix operand handling for the psl/psr family of xmm shifts/rotatesiximeow
these instructions ignored rex bits even for xmm reigsters, which is incorrect (so says xed)
2023-07-05re-correct operand order of movdq2qiximeow
2023-07-04more read_E hoistingiximeow
2023-07-04regalloc magic? no useful diff but better perf. 49.61cpi (2233ms)iximeow
2023-07-04two more test casesiximeow
2023-07-04incidental cleanup, see if inlining in evex helps/hurts (it hurts)iximeow
2023-07-04fix xbegin/xend (broken in DecodeCtx::rrr)iximeow
2023-07-04finally delete top-level modrm (50.10cpi, 2322ms)iximeow
2023-07-04begin project to hoist all read_E (perf better again! 50.21cpi)iximeow
2023-07-04fix f6 test imm lengths (perf regression :( )iximeow
2023-07-04new high score 49.89cpi (2259ms)iximeow
vex/rex prefix cleanup, finally profitable to inline read_0f*_opcode
2023-07-04more read_E cleanupiximeow
2023-07-04new struct for temporary decode context (prefix management)iximeow
2023-07-04new record: 50.56cpi (2290ms)iximeow
2023-07-04new perf record: 50.79cpi (2316ms)iximeow
2023-07-04best: 54.3cpi (2512ms)iximeow
2023-07-04new perf record: 51.88cpi (2363ms)iximeow
2023-07-04wipiximeow
2023-07-04more micro-opts...iximeow
set_embedded_instructions was unnecessarily appilied to many operand codes; this was never a correctness issue, but meant many operand decodings took a few more instruction than necessary to do nothing. setting all registers to `rax` is unnecessary, only the first register's defaulting to `rax` is effectual. this allows for not using a movabs to load initial rax state. adjust vex decoder inlining. this will be followed up by some cleanup for vex operand codes.
2023-07-04move some unlikely checks behind a branch that implies their possibilityiximeow
slightly fewer (perfectly predicted anyway) branches this way
2023-07-04fidget with read_E inlining AGAINiximeow
2023-07-04make operandcode 16b againiximeow
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