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* the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be
constructed in two ways that produce "identical" `RegSpec` that are..
not.
e.g. `RegSpec::al() != Regspec::rb(0)` even though
`RegSpec::al().name() == RegSpec::rb(0).name()`.
this corrects the `rb` constructor at least, but instructions like
`4830c0` and `30c0` still produce incompatible versions of `al`.
* also fix register numbering used explicit qword-sized RegSpec
constructors, r12 and r13 used to produce r8 and r9
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these functions had a copypaste error where the r12 and r13 versions
would create RegSpec for registers 8 and 9 instead of 12 and 13. use
correct register numbers in these macros.
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right now...
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This reverts commit 15c821a2d3fbf2fc0458090b6cc12f2ac093f075.
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not a huge improvement, but something
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these instructions ignored rex bits even for xmm reigsters, which is
incorrect (so says xed)
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vex/rex prefix cleanup, finally profitable to inline read_0f*_opcode
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