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8 hours2.1.1HEAD2.1.1no-gods-no-iximeow
8 hoursfix jrcxz/jecxz/jcxz having "two operands"iximeow
30 hours2.1.0 is real!iximeow
30 hourspush/pop width in 16/32-bit modes are receptive to operand width prefixiximeow
31 hoursdont clobber test VM control state in tests..iximeow
31 hoursreject arpl in 16-bit decodingiximeow
31 hoursreword changelogiximeow
31 hoursand some prefix helpers should be pubiximeow
31 hoursj*cxz/pusha/popa alternate size formsiximeow
these all existed since forever but the library did not distinguish them and did not provide prefix information for users to tell which had been decoded.
42 hoursenable internal asserts during fuzzingiximeow
43 hoursadapt long-mode behavior support to protected mode and real modeiximeow
along the way, fix an error: maskmov is memory read-write. additionally, operand information about {push,pop}a{,d}.
45 hoursadd behavior information for x86_64 instructionsiximeow
this is a squash of a few months' hacking, including but not limited to what eventually got extracted into https://git.iximeow.net/asmlinator/about/ the path here is generally not historically interesting, and the vast majority of this diff is very particular static data tables (BehaviorDigests and implicit operand lists) `src/long_mode/behavior.rs` will more or less be directly adapted into versions for x86-32 and x86-16, similar to the instruction decoders.
47 hours66-prefixed sha1rnds4 doesnt even realiximeow
47 hoursgpr register size in real/protected modeiximeow
47 hoursdisallow 66-prefixed sha1rnds4iximeow
47 hourspusha/popa/push-imm memory sizesiximeow
47 hourshelpers to create cr0-cr7iximeow
47 hoursworking through a bunch of avx512 stuff, regspec constructors are constiximeow
47 hourspextr*/extractpsiximeow
47 hoursfeature guard for key lockeriximeow
48 hoursinvept precisioniximeow
48 hoursmore precision for vinsert/vextract/vblendv{ps,pd}iximeow
48 hoursactually support avx/f16c in per-uarch decodingiximeow
48 hoursvmaskmovdqu, vmovq were also incorrect in some ways...iximeow
2 daysmore general avx improvementsiximeow
2 dayscleanup pass on vex-encoded instructions is going to be excitingiximeow
2 daysreport memory access size for "monitor"iximeow
2 daysmaskmov{q,dqu} memory access sizeiximeow
2 daysmore precise about 0f0d prefetch/nopiximeow
2 daysfix table management instructions' ({l,s}{g,i,l}dt) mem_sizeiximeow
these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know!
2 daysmore accurate mov seg-to-gpr operand sizeiximeow
2 dayspush/pop for segment registers has implicit memory accessiximeow
2 dayspushf, popf, enter, leave, xlat all have implicit memory accessiximeow
also add "is_masked" to operand spec
2 daysadd initial stats for disasm stats in all modesiximeow
2 daysgoodfile should use shas directly for local untagged refsiximeow
2026-02-22correct push-immediate memory access sizeiximeow
2026-02-14fair enough on those warningsiximeow
2026-02-14type aliases make some of these signatures less egregious..iximeow
2026-02-14uarch settings for apx, avx10.1, etc + nouns get capsiximeow
2025-09-29fix broken capstone_bench stuff, might delete later, idkiximeow
2025-09-29annotation description test requires `fmt`iximeow
this was missed in typical testing because either tests run with all features, no features, or fmt. there wasn't a test entry for only std, which was broken.
2025-06-02changelog should note ISA extension changesiximeow
2025-06-013dnow was still supported on K8, K10. 32-bit mode should learn about uarch ↵iximeow
tweaks too
2025-06-01describe the per-isa extensions a bit betteriximeow
2025-06-01revise_instruction is the same on all bitnesses, so macro it tooiximeow
2025-06-01DecodeEverything wasn't useful, no better than InstDecoder::default()??iximeow
2025-06-01cpu feature bits are the same across 64/32/16-bitiximeow
2025-06-01expand isa feature selection to more bitsiximeow
this is backed by the new IsaSettings trait. the existing InstDecoders are unchanged, except that they implement this new trait. also add new `DecodeEverything` structs with `IsaSettings` impls that are unconditionally set to permit anything the decoder can be configured to conditionally accept or reject. in the process, add new `_3dnow` flag and stop accepting 3dnow instructions in uarch-specific decoder settings that would not have 3dnow instructions. update AMD microarchitectures and cross-ref chip directory
2024-06-24summary description of opt work2.0.0iximeow
this empty commit reproduces a github comment that describes the work on commits from this point back to, roughly, 1.2.2. since many commits between these two points are interesting in the context of performance optimization (especially uarch-relevant tweaks), many WIP commits are preserved. as a result there is no clear squash merge, and this commit will be the next best thing. on Rust 1.68.0 and a Xeon E3-1230 V2, relative changes are measured roughly as: starting at ed4f238a4c2d860e6fadc8abeaa0cba36ed1df8a: - non-fmt ns/decode: 15ns - non-fmt instructions/decode: 94.6 - non-fmt IPC: 1.71 - fmt ns/decode+display: 91ns - fmt instructions/decode+display: 683.8 - fmt IPC: 2.035 ending at 6a5ea107475284756070614a566970fbb383c4e6 - non-fmt ns/decode: 15ns - non-fmt instructions/decode: 94.6 - non-fmt IPC: 1.71 - fmt ns/decode+display: 47ns - fmt instructions/decode+display: 329.6 - fmt IPC: 1.898 for an overall ~50% reduction in runtimes to display instructions. writing into InstructionTextBuffer reduces overhead another ~10%. -- original message follows -- this is where much of https://github.com/iximeow/yaxpeax-arch/pull/7 originated. `std::fmt` as a primary writing mechanism has.. some limitations: * https://github.com/rust-lang/rust/issues/92993#issuecomment-2028915232 * https://github.com/llvm/llvm-project/issues/87440 * https://github.com/rust-lang/rust/pull/122770 and some more interesting more fundamental limitations - writing to a `T: fmt::Write` means implementations don't know if it's possible to write bytes in reverse order (useful for printing digits) or if it's OK to write too many bytes and then only advance `len` by the correct amount (useful for copying variable-length-but-short strings like register names). these are both perfectly fine to a `String` or `Vec`, less fine to do to a file descriptor like stdout. at the same time, `Colorize` and traits depending on it are very broken, for reasons described in yaxpeax-arch. so, this adapts `yaxpeax-x86` to use the new `DisplaySink` type for writing, with optimizations where appropriate and output spans for certain kinds of tokens - registers, integers, opcodes, etc. it's not a perfect replacement for Colorize-to-ANSI-supporting-outputs but it's more flexible and i think can be made right. along the way this completes the move of `safer_unchecked` out to yaxpeax-arch (ty @5225225 it's still so useful), cleans up some docs, and comes with a few new test cases. because of the major version bump of yaxpeax-arch, and because this removes most functionality of the Colorize impl - it prints the correct words, just without coloring - this is itself a major version bump to 2.0.0. yay! this in turn is a good point to change the `Opcode` enums from being tuple-like to struct-like, and i've done so in https://github.com/iximeow/yaxpeax-x86/commit/1b8019d5b39a05c109399b8628a1082bfec79755. full notes in CHANGELOG ofc. this is notes for myself when i'm trying to remember any of this in two years :)
2024-06-24document one more stray unsafeiximeow