| Age | Commit message (Expand) | Author |
|---|
| 2026-05-08 | vex support done, starting on evex.. | iximeow |
| 2026-05-08 | working through a bunch of avx512 stuff.. | iximeow |
| 2026-05-04 | pextr*/extractps | iximeow |
| 2026-05-04 | feature guard for key locker | iximeow |
| 2026-05-03 | invept precision | iximeow |
| 2026-05-03 | vblendv{ps,pd} precision | iximeow |
| 2026-05-03 | more precision for vinsert/vextract | iximeow |
| 2026-05-03 | actually support avx/f16c in per-uarch decoding | iximeow |
| 2026-05-03 | much closer to comprehensively covering vex instructions.. | iximeow |
| 2026-05-02 | vmaskmovdqu, vmovq were also incorrect in some ways... | iximeow |
| 2026-04-30 | more general avx improvements | iximeow |
| 2026-04-23 | simd-enabled asmlinator | iximeow |
| 2026-04-23 | warnings, cleanup | iximeow |
| 2026-04-23 | start verifying vex-encoded instruction behavior | iximeow |
| 2026-04-23 | cleanup pass on vex-encoded instructions is going to be exciting | iximeow |
| 2026-04-19 | warnings, crc32 test | iximeow |
| 2026-04-19 | report memory access size for "monitor" | iximeow |
| 2026-04-19 | a few more straggler instructions | iximeow |
| 2026-04-19 | the rest of sse? | iximeow |
| 2026-04-19 | substantially more sse coverage | iximeow |
| 2026-04-17 | TODO: 32/16, maskmov{q,dqu} memory access size | iximeow |
| 2026-04-17 | more precise about 0f0d prefetch/nop | iximeow |
| 2026-04-12 | cmovcc: encode operand 2 correctly | iximeow |
| 2026-04-12 | check and support more 0fXX opcodes | iximeow |
| 2026-04-12 | sgdt/lidt/lgdt test fixes | iximeow |
| 2026-04-12 | note idt/gdt memory sizes being wrong | iximeow |
| 2026-04-12 | test table management instructions ({l,s}{g,i,l}dt) | iximeow |
| 2026-04-12 | many conditional instructions, jump, call, and start testing 0f opcodes | iximeow |
| 2026-03-29 | rip out the kvm bits into a standalone crate | iximeow |
| 2026-03-28 | full range | iximeow |
| 2026-03-28 | last few weird cases unsuitable for generic testing | iximeow |
| 2026-03-28 | handle instructions that read and write different parts of the same instruction | iximeow |
| 2026-03-28 | more behavior, the rest of two-byte instructions? | iximeow |
| 2026-03-27 | more accurate mov seg-to-gpr operand size | iximeow |
| 2026-03-27 | test infra for segment regs, push/pop small regs | iximeow |
| 2026-03-27 | push/pop for segment registers has implicit memory access | iximeow |
| 2026-03-27 | div ops, mul ops, some other | iximeow |
| 2026-03-19 | more instructions, figured out mul/imul | iximeow |
| 2026-03-09 | back at it with more instruction behaviors and carveouts | iximeow |
| 2026-03-09 | separate: more implicit operand size bits | iximeow |
| 2026-03-09 | api and more inst behavior | iximeow |
| 2026-03-09 | write/read writes operand 0 | iximeow |
| 2026-03-09 | exception vector fmt | iximeow |
| 2026-03-09 | stop relying on mmio for behavior validation | iximeow |
| 2026-03-02 | this might actually work omggggg | iximeow |
| 2026-03-02 | cleanup, document, etc | iximeow |
| 2026-03-02 | ok, gdt works... (mem16:32 means 32-bit offset THEN 16-bit selector???) | iximeow |
| 2026-02-25 | hey that's useful | iximeow |
| 2026-02-23 | set up an IDT, and try to use it, but just discover the GDT is actually broken | iximeow |
| 2026-02-23 | more expansive access behavior validation, start on implicit op lists | iximeow |
