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13 daysjustify the current max instruction lengthiximeow
this is also checked by a new fuzz target
13 daysrename most operand variants, make them structy rather than tupleyiximeow
14 daysremove yaxpeax-x86 safer_unchecked.rs, it is now in yaxpeax-archiximeow
2024-06-22extract reusable display bits into yaxpeax-arch, add a visitor fn to Operandiximeow
comes with deleting the body of impl Colorize for Operand, because we can reuse the normal operand formatting code
2024-06-21things compile again, add a few more caution signs around InstructionTextBufferiximeow
2024-06-21separate out display code further, reword comments on InstructionTextSink to ↵iximeow
be ... stern
2024-04-02display opt: mem size labels and minor segment reporting changesiximeow
for mem size labels: add one new "BUG" entry at the start of the array so `mem_size` does not need to be adjusted before being used to look up a string from the `MEM_SIZE_STRINGS` array. it's hard to measure the direct benefit of this, but it shrinks codegen size by a bit and simplfies a bit of assembly.... for segment reporting changes: stos/scas/lods do not actually need special segment override logic. instead, set their use of `es` when decoded, if appropriate. this is potentially ambiguous; in non-64bit modes the sequence `26aa` would decode as `stos` with explicit `es` prefix. this is now identical to simply decoding `aa`, which now also reports that there is an explicit `es` prefix even though there is no prefix on tne instruction. on the other hand, the prefix-reported segment now more accurately describes the memory selector through which memory accesses will happen. seems ok?
2023-12-16abnormal memory sizes for keylocker instructions are not bugsiximeow
new `does_not_decode_invalid_registers` fuzzer found other bugs! the 384-bit accesses for 128b keylocker instructions are an otherwise-unknown size and had a memory size of `BUG`. they are not bugs. give the memory size a real name.
2022-09-23Fix some typos.Bruce Mitchener
2022-04-24fix a few issues preventing no-std builds from ... buildingiximeow
this includes a `Makefile` that exercises the various crate configs. most annoyingly, several doc comments needed to grow `#[cfg(feature="fmt")]` blocks so docs continue to build with that feature enabled or disabled. carved out a way to run exhaustive tests; they should be written as `#[ignore]`, and then the makefile will run even ignored tests on the expectation that this will run the exhaustive (but slower) suite. exhaustive tests are not yet written. they'll probably involve spanning 4 byte sequences from 0 to 2^32-1.
2022-01-02Wrap unsafe functions to catch errors in debug5225225
Closes https://github.com/iximeow/yaxpeax-x86/issues/16
2021-08-21report memory sizes for push, pop, call, retiximeow
these instructions had memory sizes reported for the operand, if it was a memory operand, but for versions with non-memory operands the decoded `Instruction` would imply that non memory access would happen at all. now, decoded instructions in these cases will report a more useful memory size.
2021-07-06fix doc items, add example for use of yaxpeax_x86 by yaxpeax_arch traits1.0.3iximeow
2021-07-04update crate to rust 2018iximeow
2021-07-04add real-mode decoderiximeow
2021-07-04fix several incorrect tests and docs in 64- and 32-bit modesiximeow
2021-07-03write some dang docs, export `MemoryAccessSize` where you'll look for itiximeow
2021-07-03export long_mode as amd64, a more recognizable nameiximeow
2021-07-03factor out MemoryAccessSizeiximeow
2020-03-22yaxpeax-x86 decodes in 32-bit mode nowiximeow
2020-01-15make space for non-64bit modesiximeow
2020-01-15make x86 actually no_stdiximeow
it depended on crates that dragged in std, oops
2020-01-15add more sse2 instructions (packed shift by immediate, mostly)iximeow
really need to adjust OperandCode, almost out of one-off options...
2020-01-15add 660f6* series instructions as well as 660f70iximeow
this adds in some missing sse2 instructions in the alternate secondary opcode map. because these were missing, instructions were incorrectly decoded from the 0f opcode map, yielding mmx-operand versions of themselves (usually) there are undoubtedly more missing sse2 instructions from the 660f map.
2020-01-15no_std!!iximeow
this makes yaxpeax-x86 no_std. no externally-visible changes!
2020-01-13explicitly fail to handle WAIT prefixiximeow
2020-01-13test that instruction lengths are correctiximeow
fix several instances of incorrect instruction lengths * immediates for `mov reg, imm` and some other instructions were double-counted * lengths for vex prefixes were wrong all over the place
2020-01-13add Default impl for Instruction to track yaxpeax-archiximeow
2020-01-13de-pub some internal functionsiximeow
2020-01-12"fix warnings"iximeow
this assists many misdecodes from being totally wrong to only slightly wrong and more clear about it (rrr-selected opcodes or W-bit-selected opcodes were accidentally decoded as the first variant of their opcode) also fixes sillier warnings all over the place, and probably a few incorrectly counted lengths
2020-01-12match changes in arch to have Resulty decode, instead of Optioniximeow
2020-01-12custom hasher for regspeciximeow
for hashmaps with heavy traffic keyed on RegSpec, this can be a significant time savings
2020-01-12avx feature flag and avx/aesni instructions flagged properlyiximeow
2020-01-12fix avx bit numberiximeow
2020-01-12support aesniiximeow
this includes respecting ModRM_XXXX-style operand codes from alternate 0f opcode maps. this MAY introduce bugs where an opcode 0fXX is valid by the 0f map, invalid by the 660f map, and we see a sequence like 660fXXYY. if YY results in 0fXX being invalid by 660f, we may have to fall back to reading opcode XX as an 0f opcode, where YY needs to be re-read with the correct operand code. hopefully this doesn't actually happen...
2020-01-12support missing sse3 instructions, add tests for sse3 instructionsiximeow
2020-01-12add avx decoder flag, and a display impl showing active featuresiximeow
2020-01-12test fence instructions against different quirks modesiximeow
add enclv instruction add sse3, ssse3, sse4.1, and sse4.2 feature flags, plus a host of missing opcodes
2020-01-12initial flagging supportiximeow
2020-01-12add a slew of system-y instructions, as well as cpu quirks for amd/intel ↵iximeow
fence instructions
2020-01-12vex tests work!iximeow
2020-01-12vexiximeow
2020-01-12movs on non-byte operandsiximeow
2020-01-12that wasnt supposed to get committediximeow
2020-01-12proper movs operand supportiximeow
2020-01-12pshuf/psr/shld/shrd plus some test fixesiximeow
this makes all current non-vex/evex tests pass!!!
2020-01-12down to one failing test, for nowiximeow
2020-01-12more cvt variantsiximeow
2020-01-12improved cvts again, movd/movqiximeow
2020-01-12add pxor and some others, support mm operandsiximeow
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