| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2020-08-09 | sse4.1 instruction tests | iximeow | |
| 2020-08-09 | display bits refactor | iximeow | |
| 2020-07-26 | ssse3, some missing sse4.1, and pextrw operands | iximeow | |
| 2020-05-23 | add SHA, BMI1, and BMI2, complete XSAVE extension support | iximeow | |
| additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base | |||
| 2020-05-21 | add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensions | iximeow | |
| also add builders to get decoders appropriate for specific microarchitectures from intel and amd * low-power architectures are not yet present | |||
| 2020-05-03 | that instruction is cwd, not cbd | iximeow | |
| 2020-02-22 | fix {jmp,call} <reg>, as well as jmpf/callf | iximeow | |
| also support vmxon to finish out the f30f opcode map add tests for forms of inc/dec, as well as TODOs, as yaxpeax-x86 doesn't provide a way to distinguish different operand sizes (yet) | |||
| 2020-02-22 | support 660f sse2 instructions | iximeow | |
| this isn't quite all of sse2, but gets close. the f20f opcode map still needs some touching up. also fix `G_E_xmm_Ib` not respecting rex.r for the rrr operand | |||
| 2020-02-11 | support `in` and `out` instructions | iximeow | |
| 2020-02-11 | add `RegSpec::name` to get `&'static str` labels for registers | iximeow | |
| 2020-01-15 | make space for non-64bit modes | iximeow | |
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index : yaxpeax-x86 | |
| yaxpeax x86 decoder |
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