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path: root/src/long_mode/display.rs
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2024-04-02display: gate rep printing with a simpler checkiximeow
testing against six opcodes to see if we should print rep or repnz is a bit absurd. they are relatively rare instructions, so this is a long sequence of never-taken tests. we can avoid the whole thing in the common case by testing if there is any kind of rep prefix at all.
2024-04-02display opt: mem size labels and minor segment reporting changesiximeow
for mem size labels: add one new "BUG" entry at the start of the array so `mem_size` does not need to be adjusted before being used to look up a string from the `MEM_SIZE_STRINGS` array. it's hard to measure the direct benefit of this, but it shrinks codegen size by a bit and simplfies a bit of assembly.... for segment reporting changes: stos/scas/lods do not actually need special segment override logic. instead, set their use of `es` when decoded, if appropriate. this is potentially ambiguous; in non-64bit modes the sequence `26aa` would decode as `stos` with explicit `es` prefix. this is now identical to simply decoding `aa`, which now also reports that there is an explicit `es` prefix even though there is no prefix on tne instruction. on the other hand, the prefix-reported segment now more accurately describes the memory selector through which memory accesses will happen. seems ok?
2023-12-16fix opportunity for unhandled register synonymsiximeow
registers `al`, `cl`, `dl`, and `bl` could have two different representations - with `rex.w` and without. these two forms of `RegSpec` would not compare equal, nor has the same, so for code relying on `RegSpec` to faithfully represent a 1-1 mapping to x86 registers, these synonyms would introduce bugs in register analysis. for example, in `yaxpeax-core`, this would result in instructions writing to `rex.w al` not being visible as definitions for a future read of `!rex.w al`. fix this in `x86_64` code, add new test cases about the confusion, adjust register names to make this situation more clearly a bug, and introduce two new fuzz targets that would have helped spot this error.
2023-07-04best: 54.3cpi (2512ms)iximeow
2023-07-04line up Opcode values for simple translation from opc bytesiximeow
2023-07-04fixup: handle mnemonic ordering tooiximeow
2023-07-04pick useful numeric values for RegisterBankiximeow
these coincidentally have the general-purpose banks (rB excepted) matching their size in bytes
2022-01-12fuzz DisplayStyle::C and fix corresponding issues1.1.4iximeow
2022-01-02Wrap unsafe functions to catch errors in debug5225225
Closes https://github.com/iximeow/yaxpeax-x86/issues/16
2021-10-10support endbr{32,64}iximeow
2021-10-10consistentify doc styleiximeow
2021-10-10export `InstructionDisplayer` (#9)i509VCB
This makes generated docs refer to a type and show said type in the list of all structs rather than rustdoc showing gray text in return types. quote doc references
2021-08-21improve relative branch offset formatting for DisplayStyle::Ciximeow
2021-08-21fix negative relative branches (again!!! +- is bad!!!)iximeow
2021-08-14relative branches should be shown as $+offset, not just plain offsetiximeow
while x86 branches of immediates are all relative to PC, other architectures may have absolute branches to immediate addresses, leaving this syntax ambiguous and potentially confusing. yaxpeax prefers to write relative offsets `$+...` as a rule, so uphold that here.
2021-07-04update crate to rust 2018iximeow
2021-07-04support avx512 registers >=16iximeow
2021-07-04support xacquire/xrelease prefixingiximeow
2021-07-03document public members in long_modeiximeow
2021-07-03factor out MemoryAccessSizeiximeow
2021-07-03add tests for MemoryAccessSize, consistentify style on docsiximeow
2021-07-03support AMD `sev_snp`iximeow
2021-07-03add hresetiximeow
2021-07-03support pconfig/tmeiximeow
2021-07-03reject instructions when their opcode is `Invalid`iximeow
the evex route would allow "valid" instructions that have the opcode `invalid`. this is.. not correct.
2021-07-01reallocate OperandCode, convert disparate registers to arrayiximeow
also remove redundant assignments of operand_count and some OperandSpec, bulk-assign all registers and operands on entry to `read_instr`. this all, taken together, shaves off about 7 cycles per decode.
2021-06-28remove old movsx/movzx-related memory size hacksiximeow
2021-06-27remove support for nonexistent prefixesiximeow
2021-06-27report memory sizes for all long-mode instructionsiximeow
2021-06-26clean up avx2-related warningsiximeow
2021-06-26add long-mode avx512 support, except for compressed displacementsiximeow
2021-06-11add extensive avx and initial avx2 tests, fix several bugs and missing ↵iximeow
instructions
2021-05-16fix ShowContextual rendering error with stale data and operands, publish 0.2.20.2.2iximeow
2021-05-07update yaxpeax-arch to 0.0.5, fix interface breakagesiximeow
2021-03-21include memory sizes on inc/dec in C formatiximeow
2021-03-21add tsxldtrkiximeow
does intel know no bounds
2021-03-21add missing vpmaxuw, remove nonsense avx moviximeow
2021-03-21complete CET support, add UINTR, add missing VORP{S,D}, other cleanupiximeow
2021-03-21add waitpkg, clean up unused values, old commentsiximeow
2021-03-21add tdxiximeow
decoder flag to come
2021-03-21rewrite 0f-based instruction handlingiximeow
this is... a more significant rewrite than i expected yaxpeax-x86 to ever need. it turns out that capstone is extremely permissive about duplicative 66/f2/f3 prefixes to the point that the implemented prefex handling was unsalvageable. while this replaces the *0f* opcode tables, i haven't profiled these changes. it's possible this is a net improvement for single-byte opcodes, it could be a net loss. code size may be severely impacted. there is still work to do. but this in total gets very close to iced/xed/zydis parity, far more than before. also adds several small extensions, gfni, 3dnow, enqcmd, invpcid, some of cet, and a few missing avx instructions.
2021-03-17support several new extensions, 3dnow, and nuance in invalid operandsiximeow
2021-03-14alternate display mode for c-style expressionsiximeow
2021-03-13split ffi crate to support distinct 16, 32, and 64-bit buildsiximeow
initial work to optionally discard any instruction printing support when using `-Z build-std` to fully remove .eh_frame, a stripped long_mode_no_fmt .so is 61kb!
2021-01-15fix several missing or invalid decodings among 0f01 opcodesiximeow
* `mwaitx`, `monitorx`, `rdpru`, and `clzero` are now supported * swapgs is no longer decoded in protected mode * rdpkru and wrpkru are no longer decoded if mod bits != 11
2020-08-09support salc, get segment register numbers rightiximeow
2020-08-09unused importiximeow
2020-08-09avoid a bunch of checks in the likely display pathiximeow
rep_any will get speculated `false` quite quickly, whereas checking if the opcode is a string instruction will be costly no matter what. in the rare case rep_any is true, i don't care how costly displaying the instruction is - string instructions are relatively rare, and rep movs is typically not more than one instance when it shows up.
2020-08-09display opt, aykmiximeow
the arms of the match in regspec_label referenced tables that were not const. consequently, they would be rebuilt when reached, every time the match is incanted. this holds through even when regspec_label is inlined. each arm could be a const array for a small and easy change, but to avoid the indirect dispatch on spec.bank i've reorganized register names into a single const array and selected values for `RegisterBank` such that indices into that array can be formed. for my next trick, i may make `REG_NAMES` a `*const u8`, with indices picking offsets into the table - 8-byte offsets might do? this should compact down size a little more by removing a pointer and size qword for each string.
2020-08-09cmc and int1iximeow