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while x86 branches of immediates are all relative to PC, other
architectures may have absolute branches to immediate addresses, leaving
this syntax ambiguous and potentially confusing. yaxpeax prefers to
write relative offsets `$+...` as a rule, so uphold that here.
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the evex route would allow "valid" instructions that have the opcode
`invalid`. this is.. not correct.
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also remove redundant assignments of operand_count and some OperandSpec,
bulk-assign all registers and operands on entry to `read_instr`. this
all, taken together, shaves off about 7 cycles per decode.
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instructions
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does intel know no bounds
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decoder flag to come
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this is... a more significant rewrite than i expected yaxpeax-x86 to
ever need. it turns out that capstone is extremely permissive about
duplicative 66/f2/f3 prefixes to the point that the implemented prefex
handling was unsalvageable.
while this replaces the *0f* opcode tables, i haven't profiled these
changes. it's possible this is a net improvement for single-byte
opcodes, it could be a net loss. code size may be severely impacted.
there is still work to do.
but this in total gets very close to iced/xed/zydis parity, far more
than before.
also adds several small extensions, gfni, 3dnow, enqcmd, invpcid, some
of cet, and a few missing avx instructions.
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initial work to optionally discard any instruction printing support
when using `-Z build-std` to fully remove .eh_frame, a stripped
long_mode_no_fmt .so is 61kb!
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* `mwaitx`, `monitorx`, `rdpru`, and `clzero` are now supported
* swapgs is no longer decoded in protected mode
* rdpkru and wrpkru are no longer decoded if mod bits != 11
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rep_any will get speculated `false` quite quickly, whereas checking if
the opcode is a string instruction will be costly no matter what. in the
rare case rep_any is true, i don't care how costly displaying the
instruction is - string instructions are relatively rare, and rep movs
is typically not more than one instance when it shows up.
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the arms of the match in regspec_label referenced tables that were not
const. consequently, they would be rebuilt when reached, every time the
match is incanted. this holds through even when regspec_label is
inlined.
each arm could be a const array for a small and easy change, but to
avoid the indirect dispatch on spec.bank i've reorganized register names
into a single const array and selected values for `RegisterBank` such
that indices into that array can be formed.
for my next trick, i may make `REG_NAMES` a `*const u8`, with indices
picking offsets into the table - 8-byte offsets might do? this should
compact down size a little more by removing a pointer and size qword
for each string.
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additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base
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also add builders to get decoders appropriate for specific
microarchitectures from intel and amd
* low-power architectures are not yet present
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also support vmxon to finish out the f30f opcode map
add tests for forms of inc/dec, as well as TODOs, as yaxpeax-x86 doesn't
provide a way to distinguish different operand sizes (yet)
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this isn't quite all of sse2, but gets close. the f20f opcode map still
needs some touching up.
also fix `G_E_xmm_Ib` not respecting rex.r for the rrr operand
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