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path: root/src/long_mode/display.rs
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2021-03-17support several new extensions, 3dnow, and nuance in invalid operandsiximeow
2021-03-14alternate display mode for c-style expressionsiximeow
2021-03-13split ffi crate to support distinct 16, 32, and 64-bit buildsiximeow
initial work to optionally discard any instruction printing support when using `-Z build-std` to fully remove .eh_frame, a stripped long_mode_no_fmt .so is 61kb!
2021-01-15fix several missing or invalid decodings among 0f01 opcodesiximeow
* `mwaitx`, `monitorx`, `rdpru`, and `clzero` are now supported * swapgs is no longer decoded in protected mode * rdpkru and wrpkru are no longer decoded if mod bits != 11
2020-08-09support salc, get segment register numbers rightiximeow
2020-08-09unused importiximeow
2020-08-09avoid a bunch of checks in the likely display pathiximeow
rep_any will get speculated `false` quite quickly, whereas checking if the opcode is a string instruction will be costly no matter what. in the rare case rep_any is true, i don't care how costly displaying the instruction is - string instructions are relatively rare, and rep movs is typically not more than one instance when it shows up.
2020-08-09display opt, aykmiximeow
the arms of the match in regspec_label referenced tables that were not const. consequently, they would be rebuilt when reached, every time the match is incanted. this holds through even when regspec_label is inlined. each arm could be a const array for a small and easy change, but to avoid the indirect dispatch on spec.bank i've reorganized register names into a single const array and selected values for `RegisterBank` such that indices into that array can be formed. for my next trick, i may make `REG_NAMES` a `*const u8`, with indices picking offsets into the table - 8-byte offsets might do? this should compact down size a little more by removing a pointer and size qword for each string.
2020-08-09cmc and int1iximeow
2020-08-09vpminswiximeow
2020-08-09missing avx instriximeow
2020-08-09loop{,z,nz}/jecxziximeow
2020-08-09x87 support, plus several other missing instructionsiximeow
2020-08-09sse4.2 tests and missing instructionsiximeow
2020-08-09sse4.1 instruction testsiximeow
2020-08-09display bits refactoriximeow
2020-07-26ssse3, some missing sse4.1, and pextrw operandsiximeow
2020-05-23add SHA, BMI1, and BMI2, complete XSAVE extension supportiximeow
additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base
2020-05-21add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensionsiximeow
also add builders to get decoders appropriate for specific microarchitectures from intel and amd * low-power architectures are not yet present
2020-05-03that instruction is cwd, not cbdiximeow
2020-02-22fix {jmp,call} <reg>, as well as jmpf/callfiximeow
also support vmxon to finish out the f30f opcode map add tests for forms of inc/dec, as well as TODOs, as yaxpeax-x86 doesn't provide a way to distinguish different operand sizes (yet)
2020-02-22support 660f sse2 instructionsiximeow
this isn't quite all of sse2, but gets close. the f20f opcode map still needs some touching up. also fix `G_E_xmm_Ib` not respecting rex.r for the rrr operand
2020-02-11support `in` and `out` instructionsiximeow
2020-02-11add `RegSpec::name` to get `&'static str` labels for registersiximeow
2020-01-15make space for non-64bit modesiximeow