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2020-08-09display opt, aykmiximeow
the arms of the match in regspec_label referenced tables that were not const. consequently, they would be rebuilt when reached, every time the match is incanted. this holds through even when regspec_label is inlined. each arm could be a const array for a small and easy change, but to avoid the indirect dispatch on spec.bank i've reorganized register names into a single const array and selected values for `RegisterBank` such that indices into that array can be formed. for my next trick, i may make `REG_NAMES` a `*const u8`, with indices picking offsets into the table - 8-byte offsets might do? this should compact down size a little more by removing a pointer and size qword for each string.
2020-08-09significantly reorganize what operands are unlikelyiximeow
likely operands are now also required to have contiguous special cases 0..31. this is to avoid generating a massively sparse jump table for no reason twice - once for unlikely_operands is quite enough as-is. this will undoubtedly be a wildly annoying maintenance burden. if this pans out (initial expiriments suggest it might) then maybe a macro will do...
2020-08-09those operands are unlikelyiximeow
2020-08-09Revert "speculative code motion"iximeow
This reverts commit 21cc850afc108c147871c70240eda62ad13f34e0.
2020-08-09speculative code motioniximeow
2020-08-09Revert "bad idea"iximeow
This reverts commit 23cbcb390c723c4c39113ce93ccff89308b6623c.
2020-08-09bad ideaiximeow
2020-08-09try to special case immediates a bitiximeow
2020-08-09centralize mem_oper assignment where possibleiximeow
2020-08-09special-case lea validity check betteriximeow
2020-08-09this makes it faster i guessiximeow
2020-08-09make address_size() no longer .. necessaryiximeow
2020-08-09more speed hole!iximeow
2020-08-09drilled a new speed hole: rex doesn't need to be held through read_M or read_sibiximeow
2020-08-09crank up the inlineriximeow
2020-08-09cmc and int1iximeow
2020-08-09invalid instruction fixiximeow
2020-08-09lea speed holeiximeow
2020-08-09speed holesiximeow
2020-08-09vpminswiximeow
2020-08-09missing avx instriximeow
2020-08-09handle bad leaiximeow
2020-08-09more popiximeow
2020-08-09long instructionsiximeow
2020-08-09loop{,z,nz}/jecxziximeow
2020-08-09movabs/offsetiximeow
2020-08-09correctly handle some more invalid opcode scenariosiximeow
2020-08-09handle bad fe/ff opcode cases betteriximeow
2020-08-09fix setcc decodingiximeow
2020-08-09warnings-b-goniximeow
2020-08-09remove unused OperandCode variantsiximeow
2020-08-09more operand code cleanupiximeow
2020-08-09x87 support, plus several other missing instructionsiximeow
2020-08-09sse4.2 tests and missing instructionsiximeow
2020-08-09sse4.1 instruction testsiximeow
2020-08-09display bits refactoriximeow
2020-08-09probably notiximeow
2020-08-09congratulations on your promotioniximeow
2020-08-09simplify leaiximeow
2020-08-09change it all aroundiximeow
add `OperandCodeBuilder` to help manage allocation of enum variant values, since bit patterns of `OperandCode` are very load-bearing for decoding
2020-07-26decode lahf/sahfiximeow
2020-07-26more inline-friendliness when built without LTOiximeow
2020-07-26make read_num more amenable to inliningiximeow
deduplicate and move displacement reading make Invalid discriminant 0 to simplify "is invalid" checks (test reg, reg instead of cmp reg, imm) pad out Prefixes to 32-bits (theory being that prefix copying is now one mov instead of two)
2020-07-26ptest, pmovzxiximeow
2020-07-26ins/outsiximeow
2020-07-26bitwise ops, test cases, btriximeow
2020-07-26BTR is ev,gv not qiximeow
2020-07-26palignr and mpsabdwiximeow
2020-07-26ssse3, some missing sse4.1, and pextrw operandsiximeow
2020-07-26support upper end of 0f opcode map mmx instructionsiximeow
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