| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2023-07-23 | fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit) | iximeow | |
| 2023-07-16 | forward changes along to 32-bit decoder... | iximeow | |
| 2023-07-09 | trying to delete branches on bank size | iximeow | |
| 2023-07-09 | more matches to be mad at and turn into lookups instead | iximeow | |
| 2023-07-09 | irritated at matches | iximeow | |
| 2023-07-09 | that doesnt need to be a transmute | iximeow | |
| 2023-07-09 | changing OpcodeRecord to avoid bad use of simd | iximeow | |
| 2023-07-09 | smaller tables and err variants preserves perf, but less code/data | iximeow | |
| 2023-07-09 | table-izing these matches substantially helps (pending bugs...) | iximeow | |
| 2023-07-09 | remove very done todo | iximeow | |
| 2023-07-09 | bitpacking is_memory seems to help (surpisingly much!) | iximeow | |
| 2023-07-09 | Revert "restructuring of hotpath code, not worse but not better" | iximeow | |
| This reverts commit 15c821a2d3fbf2fc0458090b6cc12f2ac093f075. | |||
| 2023-07-09 | restructuring of hotpath code, not worse but not better | iximeow | |
| 2023-07-08 | consistently report end of prefixes/start of opcode | iximeow | |
| 2023-07-08 | todo for 2.x | iximeow | |
| 2023-07-08 | seems like this makes things a bit faster...? | iximeow | |
| 2023-07-08 | move rip-rel check to a slightly colder spot... | iximeow | |
| 2023-07-08 | actually reject lock prefixes in vex instructions | iximeow | |
| 2023-07-06 | defer assigning mem_size or operand_count too | iximeow | |
| 2023-07-06 | M_Gv should be unreachable too... | iximeow | |
| 2023-07-06 | defer initial assignment of regs and operands as much as possible | iximeow | |
| not a huge improvement, but something | |||
| 2023-07-05 | fix operand handling for the psl/psr family of xmm shifts/rotates | iximeow | |
| these instructions ignored rex bits even for xmm reigsters, which is incorrect (so says xed) | |||
| 2023-07-05 | re-correct operand order of movdq2q | iximeow | |
| 2023-07-04 | more read_E hoisting | iximeow | |
| 2023-07-04 | incidental cleanup, see if inlining in evex helps/hurts (it hurts) | iximeow | |
| 2023-07-04 | fix xbegin/xend (broken in DecodeCtx::rrr) | iximeow | |
| 2023-07-04 | finally delete top-level modrm (50.10cpi, 2322ms) | iximeow | |
| 2023-07-04 | begin project to hoist all read_E (perf better again! 50.21cpi) | iximeow | |
| 2023-07-04 | fix f6 test imm lengths (perf regression :( ) | iximeow | |
| 2023-07-04 | new high score 49.89cpi (2259ms) | iximeow | |
| vex/rex prefix cleanup, finally profitable to inline read_0f*_opcode | |||
| 2023-07-04 | more read_E cleanup | iximeow | |
| 2023-07-04 | new struct for temporary decode context (prefix management) | iximeow | |
| 2023-07-04 | new record: 50.56cpi (2290ms) | iximeow | |
| 2023-07-04 | new perf record: 50.79cpi (2316ms) | iximeow | |
| 2023-07-04 | best: 54.3cpi (2512ms) | iximeow | |
| 2023-07-04 | new perf record: 51.88cpi (2363ms) | iximeow | |
| 2023-07-04 | wip | iximeow | |
| 2023-07-04 | more micro-opts... | iximeow | |
| set_embedded_instructions was unnecessarily appilied to many operand codes; this was never a correctness issue, but meant many operand decodings took a few more instruction than necessary to do nothing. setting all registers to `rax` is unnecessary, only the first register's defaulting to `rax` is effectual. this allows for not using a movabs to load initial rax state. adjust vex decoder inlining. this will be followed up by some cleanup for vex operand codes. | |||
| 2023-07-04 | move some unlikely checks behind a branch that implies their possibility | iximeow | |
| slightly fewer (perfectly predicted anyway) branches this way | |||
| 2023-07-04 | fidget with read_E inlining AGAIN | iximeow | |
| 2023-07-04 | make operandcode 16b again | iximeow | |
| 2023-07-04 | line up Opcode values for simple translation from opc bytes | iximeow | |
| 2023-07-04 | avoid committing values to instructions until necessary, likely opc tweaks | iximeow | |
| 2023-07-04 | make base opcode map translation a bit simpler | iximeow | |
| now the bits line up with enum variants directly (hopefully..) | |||
| 2023-07-04 | store non-rex expected bank when first witnessing operand size prefix | iximeow | |
| the expectation here is that we can set a default `vqp_size` pretty cheaply (Prefixes::new is one store, on x86_64 anyway...). then, when we see an `operand_size` prefix, it's rare enough we can pay a little extra to speculate on *likely* implication, and update some state (`vqp_size` is *probably* going to be 2 because of it) accordingly. the cases where `vqp_size` would go unused and this was wasted effort are relativlely rare. on the other hand, we can't profitably give `rex` this treatment: `rex.w` would set `vqp_size` to `qword`, but rex-prefixed instructions are so often byte-size registers that updating `vqp_size` (conditionally, no less), is only break-even. so, keep a check for `rex.w` at use site, where it's only a choice between `qword` or `whatver-size-a-non-rex.w-prefixed-instruction-would-be-sized`, which has been kept up to date by speculation when detecting `operand_size`. | |||
| 2023-07-04 | fix some dancing between bank size and RegisterBank enum values | iximeow | |
| in the process, fixed a decoding bug dealing with a0/a1/a2/a3 movs (respected rex.b when rex.b should have been ignored) this seems to maybe improve runtime ever so slightly, but this is really meant as a cleanup commit more than anything. | |||
| 2023-07-04 | pick useful numeric values for RegisterBank | iximeow | |
| these coincidentally have the general-purpose banks (rB excepted) matching their size in bytes | |||
| 2023-07-04 | OperandCode as a u16 caused gross movzwl, this seems just a bit better | iximeow | |
| 2023-07-04 | try slimming down read_opc_hotpath more | iximeow | |
| 2023-03-05 | add `Opcode::is_jcc`, `Opcode::is_setcc`, and `Opcode::is_cmovcc` helpers | iximeow | |
| this request/suggestion comes from [github](https://github.com/iximeow/yaxpeax-x86/issues/29)! thank you! | |||
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