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2023-07-23fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit)iximeow
2023-07-16forward changes along to 32-bit decoder...iximeow
2023-07-09trying to delete branches on bank sizeiximeow
2023-07-09more matches to be mad at and turn into lookups insteadiximeow
2023-07-09irritated at matchesiximeow
2023-07-09that doesnt need to be a transmuteiximeow
2023-07-09changing OpcodeRecord to avoid bad use of simdiximeow
2023-07-09smaller tables and err variants preserves perf, but less code/dataiximeow
2023-07-09table-izing these matches substantially helps (pending bugs...)iximeow
2023-07-09remove very done todoiximeow
2023-07-09bitpacking is_memory seems to help (surpisingly much!)iximeow
2023-07-09Revert "restructuring of hotpath code, not worse but not better"iximeow
This reverts commit 15c821a2d3fbf2fc0458090b6cc12f2ac093f075.
2023-07-09restructuring of hotpath code, not worse but not betteriximeow
2023-07-08consistently report end of prefixes/start of opcodeiximeow
2023-07-08todo for 2.xiximeow
2023-07-08seems like this makes things a bit faster...?iximeow
2023-07-08move rip-rel check to a slightly colder spot...iximeow
2023-07-08actually reject lock prefixes in vex instructionsiximeow
2023-07-06defer assigning mem_size or operand_count tooiximeow
2023-07-06M_Gv should be unreachable too...iximeow
2023-07-06defer initial assignment of regs and operands as much as possibleiximeow
not a huge improvement, but something
2023-07-05fix operand handling for the psl/psr family of xmm shifts/rotatesiximeow
these instructions ignored rex bits even for xmm reigsters, which is incorrect (so says xed)
2023-07-05re-correct operand order of movdq2qiximeow
2023-07-04more read_E hoistingiximeow
2023-07-04incidental cleanup, see if inlining in evex helps/hurts (it hurts)iximeow
2023-07-04fix xbegin/xend (broken in DecodeCtx::rrr)iximeow
2023-07-04finally delete top-level modrm (50.10cpi, 2322ms)iximeow
2023-07-04begin project to hoist all read_E (perf better again! 50.21cpi)iximeow
2023-07-04fix f6 test imm lengths (perf regression :( )iximeow
2023-07-04new high score 49.89cpi (2259ms)iximeow
vex/rex prefix cleanup, finally profitable to inline read_0f*_opcode
2023-07-04more read_E cleanupiximeow
2023-07-04new struct for temporary decode context (prefix management)iximeow
2023-07-04new record: 50.56cpi (2290ms)iximeow
2023-07-04new perf record: 50.79cpi (2316ms)iximeow
2023-07-04best: 54.3cpi (2512ms)iximeow
2023-07-04new perf record: 51.88cpi (2363ms)iximeow
2023-07-04wipiximeow
2023-07-04more micro-opts...iximeow
set_embedded_instructions was unnecessarily appilied to many operand codes; this was never a correctness issue, but meant many operand decodings took a few more instruction than necessary to do nothing. setting all registers to `rax` is unnecessary, only the first register's defaulting to `rax` is effectual. this allows for not using a movabs to load initial rax state. adjust vex decoder inlining. this will be followed up by some cleanup for vex operand codes.
2023-07-04move some unlikely checks behind a branch that implies their possibilityiximeow
slightly fewer (perfectly predicted anyway) branches this way
2023-07-04fidget with read_E inlining AGAINiximeow
2023-07-04make operandcode 16b againiximeow
2023-07-04line up Opcode values for simple translation from opc bytesiximeow
2023-07-04avoid committing values to instructions until necessary, likely opc tweaksiximeow
2023-07-04make base opcode map translation a bit simpleriximeow
now the bits line up with enum variants directly (hopefully..)
2023-07-04store non-rex expected bank when first witnessing operand size prefixiximeow
the expectation here is that we can set a default `vqp_size` pretty cheaply (Prefixes::new is one store, on x86_64 anyway...). then, when we see an `operand_size` prefix, it's rare enough we can pay a little extra to speculate on *likely* implication, and update some state (`vqp_size` is *probably* going to be 2 because of it) accordingly. the cases where `vqp_size` would go unused and this was wasted effort are relativlely rare. on the other hand, we can't profitably give `rex` this treatment: `rex.w` would set `vqp_size` to `qword`, but rex-prefixed instructions are so often byte-size registers that updating `vqp_size` (conditionally, no less), is only break-even. so, keep a check for `rex.w` at use site, where it's only a choice between `qword` or `whatver-size-a-non-rex.w-prefixed-instruction-would-be-sized`, which has been kept up to date by speculation when detecting `operand_size`.
2023-07-04fix some dancing between bank size and RegisterBank enum valuesiximeow
in the process, fixed a decoding bug dealing with a0/a1/a2/a3 movs (respected rex.b when rex.b should have been ignored) this seems to maybe improve runtime ever so slightly, but this is really meant as a cleanup commit more than anything.
2023-07-04pick useful numeric values for RegisterBankiximeow
these coincidentally have the general-purpose banks (rB excepted) matching their size in bytes
2023-07-04OperandCode as a u16 caused gross movzwl, this seems just a bit betteriximeow
2023-07-04try slimming down read_opc_hotpath moreiximeow
2023-03-05add `Opcode::is_jcc`, `Opcode::is_setcc`, and `Opcode::is_cmovcc` helpersiximeow
this request/suggestion comes from [github](https://github.com/iximeow/yaxpeax-x86/issues/29)! thank you!
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