| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2024-06-24 | rename most operand variants, make them structy rather than tupley | iximeow | |
| 2024-06-23 | remove selects_cs(), cs() now does the right thing | iximeow | |
| 2024-06-23 | fix several sources of dead code warnings in various crate configs | iximeow | |
| 2024-06-23 | remove yaxpeax-x86 safer_unchecked.rs, it is now in yaxpeax-arch | iximeow | |
| 2024-06-23 | cfg_attr wants feature, not features plural | iximeow | |
| 2024-06-23 | add additional `call` test cases | iximeow | |
| fix 32-bit 66-prefixed ff /2 call not having 16-bit operands fix momentary regression in rendering `call` instructions to string | |||
| 2024-06-23 | centralize unsafe claims and better validate | iximeow | |
| 2024-06-23 | InstructionTextBuffer is only present with alloc (new crate flag) | iximeow | |
| 2024-06-22 | extract reusable display bits into yaxpeax-arch, add a visitor fn to Operand | iximeow | |
| comes with deleting the body of impl Colorize for Operand, because we can reuse the normal operand formatting code | |||
| 2024-06-21 | things compile again, add a few more caution signs around InstructionTextBuffer | iximeow | |
| 2024-06-21 | separate out display code further, reword comments on InstructionTextSink to ↵ | iximeow | |
| be ... stern | |||
| 2024-06-20 | starting to get new DisplaySink stuff ready to extract... | iximeow | |
| 2024-06-19 | configurable inlining to help with opts | iximeow | |
| 2024-06-18 | enough infratructure to avoid bounds checks, at incredible user cost | iximeow | |
| 2024-06-13 | use a bit of Opcode to indicate rep/repne applicability | iximeow | |
| this reduces a `slice::contains` to a single bit test, and regroups prefix printing to deduplicate checks of the `rep` prefix seemingly this reduces instruction counts by about 1%, cycles by 0.3% or so. | |||
| 2024-04-02 | lets see how a visitor for operands works out here... | iximeow | |
| 2024-04-02 | swap test order for segment override applicability | iximeow | |
| it is almost always the case that self.prefixes.segment == Segment::DS, meaning testing for it first avoids checking `self.operands[op].is_memory()` later. this overall avoids a few instructions in the typical path, rather than checking `is_memory()` first (which would always be true in the places this function is called from) | |||
| 2024-04-02 | display opt: mem size labels and minor segment reporting changes | iximeow | |
| for mem size labels: add one new "BUG" entry at the start of the array so `mem_size` does not need to be adjusted before being used to look up a string from the `MEM_SIZE_STRINGS` array. it's hard to measure the direct benefit of this, but it shrinks codegen size by a bit and simplfies a bit of assembly.... for segment reporting changes: stos/scas/lods do not actually need special segment override logic. instead, set their use of `es` when decoded, if appropriate. this is potentially ambiguous; in non-64bit modes the sequence `26aa` would decode as `stos` with explicit `es` prefix. this is now identical to simply decoding `aa`, which now also reports that there is an explicit `es` prefix even though there is no prefix on tne instruction. on the other hand, the prefix-reported segment now more accurately describes the memory selector through which memory accesses will happen. seems ok? | |||
| 2023-12-16 | fix hreset being disassembled as having second operand of "Nothing" | iximeow | |
| just report it having one operand... | |||
| 2023-12-16 | fix incorrect register class names in long_mode1.2.1 | iximeow | |
| also adjust changelog for a 1.2.1 version again, no new interfaces to go with these bugfixes. | |||
| 2023-12-16 | fix opportunity for unhandled register synonyms | iximeow | |
| registers `al`, `cl`, `dl`, and `bl` could have two different representations - with `rex.w` and without. these two forms of `RegSpec` would not compare equal, nor has the same, so for code relying on `RegSpec` to faithfully represent a 1-1 mapping to x86 registers, these synonyms would introduce bugs in register analysis. for example, in `yaxpeax-core`, this would result in instructions writing to `rex.w al` not being visible as definitions for a future read of `!rex.w al`. fix this in `x86_64` code, add new test cases about the confusion, adjust register names to make this situation more clearly a bug, and introduce two new fuzz targets that would have helped spot this error. | |||
| 2023-12-15 | more RegSpec constructor validation, fix bug in x86_64 1b reg specs | iximeow | |
| * the first four 1-byte registers, `al`, `cl`, `dl`, `bl`, can be constructed in two ways that produce "identical" `RegSpec` that are.. not. e.g. `RegSpec::al() != Regspec::rb(0)` even though `RegSpec::al().name() == RegSpec::rb(0).name()`. this corrects the `rb` constructor at least, but instructions like `4830c0` and `30c0` still produce incompatible versions of `al`. * also fix register numbering used explicit qword-sized RegSpec constructors, r12 and r13 used to produce r8 and r9 | |||
| 2023-12-15 | fix incorrect register numbers in r12/r13 RegSpec constructor functions | Dongjia "toka" Zhang | |
| these functions had a copypaste error where the r12 and r13 versions would create RegSpec for registers 8 and 9 instead of 12 and 13. use correct register numbers in these macros. | |||
| 2023-07-24 | fix handling of lar/lsl source register | iximeow | |
| 2023-07-23 | fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit) | iximeow | |
| 2023-07-16 | forward changes along to 32-bit decoder... | iximeow | |
| 2023-07-09 | trying to delete branches on bank size | iximeow | |
| 2023-07-09 | more matches to be mad at and turn into lookups instead | iximeow | |
| 2023-07-09 | irritated at matches | iximeow | |
| 2023-07-09 | that doesnt need to be a transmute | iximeow | |
| 2023-07-09 | changing OpcodeRecord to avoid bad use of simd | iximeow | |
| 2023-07-09 | smaller tables and err variants preserves perf, but less code/data | iximeow | |
| 2023-07-09 | table-izing these matches substantially helps (pending bugs...) | iximeow | |
| 2023-07-09 | remove very done todo | iximeow | |
| 2023-07-09 | bitpacking is_memory seems to help (surpisingly much!) | iximeow | |
| 2023-07-09 | Revert "restructuring of hotpath code, not worse but not better" | iximeow | |
| This reverts commit 15c821a2d3fbf2fc0458090b6cc12f2ac093f075. | |||
| 2023-07-09 | restructuring of hotpath code, not worse but not better | iximeow | |
| 2023-07-08 | consistently report end of prefixes/start of opcode | iximeow | |
| 2023-07-08 | todo for 2.x | iximeow | |
| 2023-07-08 | seems like this makes things a bit faster...? | iximeow | |
| 2023-07-08 | move rip-rel check to a slightly colder spot... | iximeow | |
| 2023-07-08 | actually reject lock prefixes in vex instructions | iximeow | |
| 2023-07-06 | defer assigning mem_size or operand_count too | iximeow | |
| 2023-07-06 | M_Gv should be unreachable too... | iximeow | |
| 2023-07-06 | defer initial assignment of regs and operands as much as possible | iximeow | |
| not a huge improvement, but something | |||
| 2023-07-05 | fix operand handling for the psl/psr family of xmm shifts/rotates | iximeow | |
| these instructions ignored rex bits even for xmm reigsters, which is incorrect (so says xed) | |||
| 2023-07-05 | re-correct operand order of movdq2q | iximeow | |
| 2023-07-04 | more read_E hoisting | iximeow | |
| 2023-07-04 | incidental cleanup, see if inlining in evex helps/hurts (it hurts) | iximeow | |
| 2023-07-04 | fix xbegin/xend (broken in DecodeCtx::rrr) | iximeow | |
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index : yaxpeax-x86 | |
| yaxpeax x86 decoder |
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