yaxpeax-x86 - yaxpeax x86 decoder

Age	Commit message (Collapse)	Author
8 hours	add behavior information for x86_64 instructions	iximeow
	this is a squash of a few months' hacking, including but not limited to what eventually got extracted into https://git.iximeow.net/asmlinator/about/ the path here is generally not historically interesting, and the vast majority of this diff is very particular static data tables (BehaviorDigests and implicit operand lists) `src/long_mode/behavior.rs` will more or less be directly adapted into versions for x86-32 and x86-16, similar to the instruction decoders.
11 hours	actually support avx/f16c in per-uarch decoding	iximeow

2025-06-01	3dnow was still supported on K8, K10. 32-bit mode should learn about uarch ↵	iximeow
	tweaks too
2025-06-01	expand isa feature selection to more bits	iximeow
	this is backed by the new IsaSettings trait. the existing InstDecoders are unchanged, except that they implement this new trait. also add new `DecodeEverything` structs with `IsaSettings` impls that are unconditionally set to permit anything the decoder can be configured to conditionally accept or reject. in the process, add new `_3dnow` flag and stop accepting 3dnow instructions in uarch-specific decoder settings that would not have 3dnow instructions. update AMD microarchitectures and cross-ref chip directory
2021-07-04	update crate to rust 2018	iximeow

2021-05-31	fix typo	iximeow

2020-07-18	intel supported cmpxchg16b from the first x86_64 architecture	iximeow

2020-05-23	fix docs up, fix the spelling of penryn0.0.13	iximeow

2020-05-23	add SHA, BMI1, and BMI2, complete XSAVE extension support	iximeow
	additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base
2020-05-21	add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensions	iximeow
	also add builders to get decoders appropriate for specific microarchitectures from intel and amd * low-power architectures are not yet present