Age | Commit message (Collapse) | Author | |
---|---|---|---|
2023-07-04 | more micro-opts... | iximeow | |
set_embedded_instructions was unnecessarily appilied to many operand codes; this was never a correctness issue, but meant many operand decodings took a few more instruction than necessary to do nothing. setting all registers to `rax` is unnecessary, only the first register's defaulting to `rax` is effectual. this allows for not using a movabs to load initial rax state. adjust vex decoder inlining. this will be followed up by some cleanup for vex operand codes. | |||
2023-07-04 | fix some dancing between bank size and RegisterBank enum values | iximeow | |
in the process, fixed a decoding bug dealing with a0/a1/a2/a3 movs (respected rex.b when rex.b should have been ignored) this seems to maybe improve runtime ever so slightly, but this is really meant as a cleanup commit more than anything. | |||
2021-08-22 | bump to yaxpeax-arch 0.2.7 and proper field description support1.1.0 | iximeow | |
2021-08-21 | report barebones decoder annotation for vex-coded instructions | iximeow | |
2021-08-21 | extend annotation reporting to 32- and 16-bit modes, kinda | iximeow | |
2021-07-04 | handle vzeroupper/vzeroall, reject vzero* with nonzero vvvv | iximeow | |
2021-07-04 | fix several incorrect tests and docs in 64- and 32-bit modes | iximeow | |
2021-07-03 | document public members in long_mode | iximeow | |
2021-07-03 | be more strict about denying invalid operands | iximeow | |
2021-07-01 | reallocate OperandCode, convert disparate registers to array | iximeow | |
also remove redundant assignments of operand_count and some OperandSpec, bulk-assign all registers and operands on entry to `read_instr`. this all, taken together, shaves off about 7 cycles per decode. | |||
2021-07-01 | update yaxpeax-x86 to yaxpeax-arch 0.1.0 interfaces | iximeow | |
2021-06-29 | fix several lingering mem_size discrepancies | iximeow | |
2021-06-28 | remove a few operand cases | iximeow | |
vex decoding is really intended to avoid explosions in code size more than anything... | |||
2021-06-28 | round out x86_32 support - avx2, avx, memory sizes | iximeow | |
2021-06-28 | protected mode memory sizes | iximeow | |
also some long-mode cleanup in corresponding areas | |||
2021-06-27 | report memory sizes for all long-mode instructions | iximeow | |
2021-06-26 | clean up avx2-related warnings | iximeow | |
2021-06-12 | finish up long mode avx2 | iximeow | |
2021-06-11 | add extensive avx and initial avx2 tests, fix several bugs and missing ↵ | iximeow | |
instructions | |||
2021-03-21 | fix potential successful decodes with Opcode::Invalid | iximeow | |
vmov* are.. somehow messed up too | |||
2021-03-21 | add missing vpmaxuw, remove nonsense avx mov | iximeow | |
2021-03-21 | complete CET support, add UINTR, add missing VORP{S,D}, other cleanup | iximeow | |
2021-03-21 | rewrite 0f-based instruction handling | iximeow | |
this is... a more significant rewrite than i expected yaxpeax-x86 to ever need. it turns out that capstone is extremely permissive about duplicative 66/f2/f3 prefixes to the point that the implemented prefex handling was unsalvageable. while this replaces the *0f* opcode tables, i haven't profiled these changes. it's possible this is a net improvement for single-byte opcodes, it could be a net loss. code size may be severely impacted. there is still work to do. but this in total gets very close to iced/xed/zydis parity, far more than before. also adds several small extensions, gfni, 3dnow, enqcmd, invpcid, some of cet, and a few missing avx instructions. | |||
2020-08-09 | no more incomplete decoder for vex instructions | iximeow | |
for now | |||
2020-08-09 | support four-reg operand forms, new tests | iximeow | |
2020-08-09 | vinserti128 | iximeow | |
2020-08-09 | vextractf128 | iximeow | |
2020-08-09 | vpsrlq | iximeow | |
2020-08-09 | vpminsw | iximeow | |
2020-08-09 | vpermq (avx2) | iximeow | |
2020-08-09 | vpsrlw avx | iximeow | |
2020-08-09 | missing avx instr | iximeow | |
2020-08-09 | probably not | iximeow | |
2020-05-23 | add SHA, BMI1, and BMI2, complete XSAVE extension support | iximeow | |
additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base | |||
2020-02-22 | support most avx operand codes | iximeow | |
avx is still incomplete, but less so avx is still practically untested | |||
2020-01-15 | make space for non-64bit modes | iximeow | |