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path: root/src/long_mode/vex.rs
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2021-08-21extend annotation reporting to 32- and 16-bit modes, kindaiximeow
2021-07-04handle vzeroupper/vzeroall, reject vzero* with nonzero vvvviximeow
2021-07-04fix several incorrect tests and docs in 64- and 32-bit modesiximeow
2021-07-03document public members in long_modeiximeow
2021-07-03be more strict about denying invalid operandsiximeow
2021-07-01reallocate OperandCode, convert disparate registers to arrayiximeow
also remove redundant assignments of operand_count and some OperandSpec, bulk-assign all registers and operands on entry to `read_instr`. this all, taken together, shaves off about 7 cycles per decode.
2021-07-01update yaxpeax-x86 to yaxpeax-arch 0.1.0 interfacesiximeow
2021-06-29fix several lingering mem_size discrepanciesiximeow
2021-06-28remove a few operand casesiximeow
vex decoding is really intended to avoid explosions in code size more than anything...
2021-06-28round out x86_32 support - avx2, avx, memory sizesiximeow
2021-06-28protected mode memory sizesiximeow
also some long-mode cleanup in corresponding areas
2021-06-27report memory sizes for all long-mode instructionsiximeow
2021-06-26clean up avx2-related warningsiximeow
2021-06-12finish up long mode avx2iximeow
2021-06-11add extensive avx and initial avx2 tests, fix several bugs and missing ↵iximeow
instructions
2021-03-21fix potential successful decodes with Opcode::Invalidiximeow
vmov* are.. somehow messed up too
2021-03-21add missing vpmaxuw, remove nonsense avx moviximeow
2021-03-21complete CET support, add UINTR, add missing VORP{S,D}, other cleanupiximeow
2021-03-21rewrite 0f-based instruction handlingiximeow
this is... a more significant rewrite than i expected yaxpeax-x86 to ever need. it turns out that capstone is extremely permissive about duplicative 66/f2/f3 prefixes to the point that the implemented prefex handling was unsalvageable. while this replaces the *0f* opcode tables, i haven't profiled these changes. it's possible this is a net improvement for single-byte opcodes, it could be a net loss. code size may be severely impacted. there is still work to do. but this in total gets very close to iced/xed/zydis parity, far more than before. also adds several small extensions, gfni, 3dnow, enqcmd, invpcid, some of cet, and a few missing avx instructions.
2020-08-09no more incomplete decoder for vex instructionsiximeow
for now
2020-08-09support four-reg operand forms, new testsiximeow
2020-08-09vinserti128iximeow
2020-08-09vextractf128iximeow
2020-08-09vpsrlqiximeow
2020-08-09vpminswiximeow
2020-08-09vpermq (avx2)iximeow
2020-08-09vpsrlw avxiximeow
2020-08-09missing avx instriximeow
2020-08-09probably notiximeow
2020-05-23add SHA, BMI1, and BMI2, complete XSAVE extension supportiximeow
additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base
2020-02-22support most avx operand codesiximeow
avx is still incomplete, but less so avx is still practically untested
2020-01-15make space for non-64bit modesiximeow