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these instructions, it turns out, have fixed operand size based on CPU
execution mode and regardless of prefixes. good to know!
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tweaks too
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this is backed by the new IsaSettings trait. the existing InstDecoders
are unchanged, except that they implement this new trait.
also add new `DecodeEverything` structs with `IsaSettings` impls that
are unconditionally set to permit anything the decoder can be configured
to conditionally accept or reject.
in the process, add new `_3dnow` flag and stop accepting 3dnow
instructions in uarch-specific decoder settings that would not have
3dnow instructions.
update AMD microarchitectures and cross-ref chip directory
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this is also checked by a new fuzz target
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fix 32-bit 66-prefixed ff /2 call not having 16-bit operands
fix momentary regression in rendering `call` instructions to string
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