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5 daysdocs, cleanupinst-behavioriximeow
5 daysadjust test framework to support complex ops, some other cleanupiximeow
also fix swapped BehaviorDigest order. that's scary..
6 daysbehavior feature, also shrink 40kb from behavior additionsiximeow
6 daysso much more docsiximeow
6 dayswarning fixiximeow
9 daysadd behavior fuzzing, fix some stuff it noticediximeow
12 daysthe rest of x86-64 behaviors. so far.iximeow
12 dayseven more EVEX encoding precision, regspec constructors are constiximeow
2026-05-08vex support done, starting on evex..iximeow
2026-05-04pextr*/extractpsiximeow
2026-05-03vblendv{ps,pd} precisioniximeow
2026-05-03more precision for vinsert/vextractiximeow
2026-05-03actually support avx/f16c in per-uarch decodingiximeow
2026-05-03much closer to comprehensively covering vex instructions..iximeow
2026-05-02vmaskmovdqu, vmovq were also incorrect in some ways...iximeow
2026-04-30more general avx improvementsiximeow
2026-04-23start verifying vex-encoded instruction behavioriximeow
2026-04-23cleanup pass on vex-encoded instructions is going to be excitingiximeow
2026-04-19report memory access size for "monitor"iximeow
2026-04-19a few more straggler instructionsiximeow
2026-04-19the rest of sse?iximeow
2026-04-19substantially more sse coverageiximeow
2026-04-17TODO: 32/16, maskmov{q,dqu} memory access sizeiximeow
2026-04-17more precise about 0f0d prefetch/nopiximeow
2026-04-12cmovcc: encode operand 2 correctlyiximeow
2026-04-12check and support more 0fXX opcodesiximeow
2026-04-12test table management instructions ({l,s}{g,i,l}dt)iximeow
these instructions, it turns out, have fixed operand size based on CPU execution mode and regardless of prefixes. good to know!
2026-04-12many conditional instructions, jump, call, and start testing 0f opcodesiximeow
2026-03-28more behavior, the rest of two-byte instructions?iximeow
2026-03-27more accurate mov seg-to-gpr operand sizeiximeow
2026-03-27push/pop for segment registers has implicit memory accessiximeow
2026-03-27div ops, mul ops, some otheriximeow
2026-03-19more instructions, figured out mul/imuliximeow
2026-03-09back at it with more instruction behaviors and carveoutsiximeow
2026-03-09separate: more implicit operand size bitsiximeow
2026-03-09api and more inst behavioriximeow
2026-03-09write/read writes operand 0iximeow
2026-03-09exception vector fmtiximeow
2026-03-02this might actually work omgggggiximeow
2026-02-25hey that's usefuliximeow
2026-02-23more expansive access behavior validation, start on implicit op listsiximeow
2026-02-23visit flags changes, tests caught a bug!iximeow
2026-02-23draftiximeow
2026-02-22correct push-immediate memory access sizeHEADno-gods-no-iximeow
2026-02-14fair enough on those warningsiximeow
2026-02-14type aliases make some of these signatures less egregious..iximeow
2026-02-14uarch settings for apx, avx10.1, etc + nouns get capsiximeow
2025-06-013dnow was still supported on K8, K10. 32-bit mode should learn about uarch ↵iximeow
tweaks too
2025-06-01describe the per-isa extensions a bit betteriximeow
2025-06-01revise_instruction is the same on all bitnesses, so macro it tooiximeow
generated by cgit v1.1 at 2026-05-22 14:05:48 +0000