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AgeCommit message (Expand)Author
2024-06-18move away from fmt for visit_i64 and displacements tooiximeow
2024-06-18less integer formatting in operandsiximeow
2024-06-18a few more accurate hintsiximeow
2024-06-18helper to clear BigEnoughStringiximeow
2024-06-18figuring out how to handle short variable-size stringsiximeow
2024-06-18enough infratructure to avoid bounds checks, at incredible user costiximeow
2024-06-17add token spans for some registersiximeow
2024-06-17might be an ok way to redesign colorization....iximeow
2024-06-16use less of core::fmt, write by handiximeow
2024-06-16remove branch better handled elsewhereiximeow
2024-06-16move to shared (safe) impl of RelativeBranchPrinteriximeow
2024-06-16commit unshippable wildly unsafe asm-filled printing codeiximeow
2024-06-16adapting contextualize_intel to use new operand visitor stuffiximeow
2024-06-13use a bit of Opcode to indicate rep/repne applicabilityiximeow
2024-04-02display: remove some pointless checksiximeow
2024-04-02less write, more write_striximeow
2024-04-02lets see how a visitor for operands works out here...iximeow
2024-04-02display: gate rep printing with a simpler checkiximeow
2024-04-02swap test order for segment override applicabilityiximeow
2024-04-02display opt: mem size labels and minor segment reporting changesiximeow
2023-12-16fix hreset being disassembled as having second operand of "Nothing"iximeow
2023-12-16fix incorrect register class names in long_mode1.2.1iximeow
2023-12-16fix opportunity for unhandled register synonymsiximeow
2023-12-15more RegSpec constructor validation, fix bug in x86_64 1b reg specsiximeow
2023-12-15fix incorrect register numbers in r12/r13 RegSpec constructor functionsDongjia "toka" Zhang
2023-07-24fix handling of lar/lsl source registeriximeow
2023-07-23fix inconsistently-poreted memory access size of vcvt{,t}{sd,si}iximeow
2023-07-23fix + better test cvttsd2si+cvtsd2si (misdecode under 64-bit)iximeow
2023-07-16forward changes along to 32-bit decoder...iximeow
2023-07-09trying to delete branches on bank sizeiximeow
2023-07-09more matches to be mad at and turn into lookups insteadiximeow
2023-07-09irritated at matchesiximeow
2023-07-09that doesnt need to be a transmuteiximeow
2023-07-09changing OpcodeRecord to avoid bad use of simdiximeow
2023-07-09smaller tables and err variants preserves perf, but less code/dataiximeow
2023-07-09table-izing these matches substantially helps (pending bugs...)iximeow
2023-07-09remove very done todoiximeow
2023-07-09bitpacking is_memory seems to help (surpisingly much!)iximeow
2023-07-09Revert "restructuring of hotpath code, not worse but not better"iximeow
2023-07-09restructuring of hotpath code, not worse but not betteriximeow
2023-07-08consistently report end of prefixes/start of opcodeiximeow
2023-07-08todo for 2.xiximeow
2023-07-08seems like this makes things a bit faster...?iximeow
2023-07-08move rip-rel check to a slightly colder spot...iximeow
2023-07-08actually reject lock prefixes in vex instructionsiximeow
2023-07-08fix v(p)gather situations, get vex tests passing againiximeow
2023-07-06defer assigning mem_size or operand_count tooiximeow
2023-07-06M_Gv should be unreachable too...iximeow
2023-07-06defer initial assignment of regs and operands as much as possibleiximeow
2023-07-05fix operand handling for the psl/psr family of xmm shifts/rotatesiximeow