aboutsummaryrefslogtreecommitdiff
path: root/src/protected_mode/display.rs
AgeCommit message (Collapse)Author
2021-07-04support avx512 registers >=16iximeow
2021-07-04support xacquire/xrelease prefixingiximeow
2021-07-04fix several incorrect tests and docs in 64- and 32-bit modesiximeow
2021-07-03document public members in long_modeiximeow
2021-07-03factor out MemoryAccessSizeiximeow
2021-07-03support AMD `sev_snp`iximeow
2021-07-03clean up x86_32 and make interfaces match x86_64iximeow
2021-07-03add hresetiximeow
2021-07-03support pconfig/tmeiximeow
2021-06-28remove old movsx/movzx-related memory size hacksiximeow
2021-06-28round out x86_32 support - avx2, avx, memory sizesiximeow
2021-06-28protected mode memory sizesiximeow
also some long-mode cleanup in corresponding areas
2021-06-27protected-mode avx512iximeow
2021-05-07update yaxpeax-arch to 0.0.5, fix interface breakagesiximeow
2021-03-22and clean up some warningsiximeow
2021-03-22port long-mode decoder updates to protected-modeiximeow
2021-01-15fix several missing or invalid decodings among 0f01 opcodesiximeow
* `mwaitx`, `monitorx`, `rdpru`, and `clzero` are now supported * swapgs is no longer decoded in protected mode * rdpkru and wrpkru are no longer decoded if mod bits != 11
2020-08-09support salc, get segment register numbers rightiximeow
2020-08-09add 32-bit-only instructionsiximeow
2020-08-09port updates to protected-mode decoderiximeow
2020-05-23add SHA, BMI1, and BMI2, complete XSAVE extension supportiximeow
additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base
2020-05-21add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensionsiximeow
also add builders to get decoders appropriate for specific microarchitectures from intel and amd * low-power architectures are not yet present
2020-05-03that instruction is cwd, not cbdiximeow
2020-03-22yaxpeax-x86 decodes in 32-bit mode nowiximeow
generated by cgit v1.1 at 2024-11-01 09:29:10 +0000