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path: root/src/protected_mode/mod.rs
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2021-07-04update crate to rust 2018iximeow
2021-07-04support xacquire/xrelease prefixingiximeow
2021-07-0416-bit addressing in protected mode may see avx512 masks tooiximeow
2021-07-04fix several incorrect tests and docs in 64- and 32-bit modesiximeow
2021-07-03update protected_mode to match long_mode docs, apisiximeow
2021-07-03update DecodeError implsiximeow
2021-07-03document public members in long_modeiximeow
2021-07-03write some dang docs, export `MemoryAccessSize` where you'll look for itiximeow
2021-07-03more carefully test mmx operand sizesiximeow
2021-07-03factor out MemoryAccessSizeiximeow
2021-07-03add tests for MemoryAccessSize, consistentify style on docsiximeow
2021-07-03be more strict about denying invalid operandsiximeow
2021-07-03do not reject prefixed sgdt, add a TODO for xopiximeow
not that xop will ever be wanted, rip
2021-07-03support AMD `sev_snp`iximeow
2021-07-03clean up x86_32 and make interfaces match x86_64iximeow
2021-07-03prefixes on 0f01-series opcodes are more strictiximeow
2021-07-03add hresetiximeow
2021-07-03port over x86_64 improvements to x86_32iximeow
2021-07-03support pconfig/tmeiximeow
2021-07-02intel keylocker instructions that access memory have memory access sizesiximeow
2021-07-02fix several strict rejection for severaliximeow
2021-07-01reallocate OperandCode, convert disparate registers to arrayiximeow
also remove redundant assignments of operand_count and some OperandSpec, bulk-assign all registers and operands on entry to `read_instr`. this all, taken together, shaves off about 7 cycles per decode.
2021-07-01update yaxpeax-x86 to yaxpeax-arch 0.1.0 interfacesiximeow
2021-06-29fix several lingering mem_size discrepanciesiximeow
2021-06-28remove old movsx/movzx-related memory size hacksiximeow
2021-06-28round out x86_32 support - avx2, avx, memory sizesiximeow
2021-06-28protected mode memory sizesiximeow
also some long-mode cleanup in corresponding areas
2021-06-27protected-mode avx512iximeow
2021-06-26awkwardiximeow
i really didnt know rust could do this
2021-05-07remove dead OperandSpec variantsiximeow
2021-03-22and clean up some warningsiximeow
2021-03-22port long-mode decoder updates to protected-modeiximeow
2021-03-21make Opcode, Operand, and DecodeError non_exhaustiveiximeow
in the future these can and will change (new operands, new instructions) and i would prefer they not be major breaking changes. applications can ignore them and probably do undesired variants anyway. if you want to write a 1120-variant match, are you me? why would you do this
2021-01-15support xchg AX/reg0.1.5iximeow
2021-01-15fix several missing or invalid decodings among 0f01 opcodesiximeow
* `mwaitx`, `monitorx`, `rdpru`, and `clzero` are now supported * swapgs is no longer decoded in protected mode * rdpkru and wrpkru are no longer decoded if mod bits != 11
2020-10-27fix misdecode of instructions in opcode 0x800.1.3iximeow
2020-08-15add RegSpec constructors, consts, and const fns0.1.2iximeow
2020-08-15add register class constants to allow reasoning about register operands0.1.1iximeow
also bump to 0.1.1
2020-08-09inaugural 0.1.0 release!0.1.0iximeow
add doc comments for public items, record changelog, and lets ship this!!
2020-08-09adjust public interface: public items should all be stableiximeow
`OperandCode` (obviously) wildly varies depending on how i feel on a given week, so it's now hidden to avoid people depending on numerical values of its discriminants. `RegisterBank` got a similar treatment with a new `RegisterClass` struct that's suitable for public use.
2020-08-09reject instructions made invalid by lock prefixesiximeow
2020-08-09support salc, get segment register numbers rightiximeow
2020-08-09add 32-bit-only instructionsiximeow
2020-08-09port updates to protected-mode decoderiximeow
2020-05-23add SHA, BMI1, and BMI2, complete XSAVE extension supportiximeow
additionally: cmpcxchg{8,16}b, rdrand, rdseed, rdpid, {rd,wr}{fs,gs}base
2020-05-21add sha, lzcnt, tsx, f16c, svm, movbe, adx, and prefetchw extensionsiximeow
also add builders to get decoders appropriate for specific microarchitectures from intel and amd * low-power architectures are not yet present
2020-05-03"is there a rep prefix" is something people need to be able to askiximeow
2020-05-03add width() to ask width of an x86 operandiximeow
this is largely wrong for memory operands, which require more invasive changes
2020-05-03that instruction is cwd, not cbdiximeow
2020-05-03bump yaxpeax-arch to 0.0.4, use AddressDiff, fix warnings in ffiiximeow